drm/msm/dpu1: Account for DSC's bits_per_pixel having 4 fractional bits

According to the comment this DPU register contains the bits per pixel
as a 6.4 fractional value, conveniently matching the contents of
bits_per_pixel in struct drm_dsc_config which also uses 4 fractional
bits.  However, the downstream source this implementation was
copy-pasted from has its bpp field stored _without_ fractional part.

This makes the entire convoluted math obsolete as it is impossible to
pull those 4 fractional bits out of thin air, by somehow trying to reuse
the lowest 2 bits of a non-fractional bpp (lsb = bpp % 4??).

The rest of the code merely attempts to keep the integer part a multiple
of 4, which is rendered useless thanks to data |= dsc->bits_per_pixel <<
12; already filling up those bits anyway (but not on downstream).

Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/508946/
Link: https://lore.kernel.org/r/20221026182824.876933-10-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index f2ddcfb..3662df6 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -42,7 +42,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
                              u32 initial_lines)
 {
        struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
-       u32 data, lsb, bpp;
+       u32 data;
        u32 slice_last_group_size;
        u32 det_thresh_flatness;
        bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
@@ -56,14 +56,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
        data = (initial_lines << 20);
        data |= ((slice_last_group_size - 1) << 18);
        /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
-       data |= dsc->bits_per_pixel << 12;
-       lsb = dsc->bits_per_pixel % 4;
-       bpp = dsc->bits_per_pixel / 4;
-       bpp *= 4;
-       bpp <<= 4;
-       bpp |= lsb;
-
-       data |= bpp << 8;
+       data |= (dsc->bits_per_pixel << 8);
        data |= (dsc->block_pred_enable << 7);
        data |= (dsc->line_buf_depth << 3);
        data |= (dsc->simple_422 << 2);