+2018-10-19 Tamar Christina <tamar.christina@arm.com>
+
+ * testsuite/gas/arm/undefined-insn-arm.d: New test.
+ * testsuite/gas/arm/undefined-insn-thumb.d: New test.
+ * testsuite/gas/arm/undefined-insn.s: New test.
+
2018-10-19 Fredrik Noring <noring@nocrew.org>
* testsuite/gas/mips/r5900.s: Extend the R5900 short loop fix
--- /dev/null
+#name: Undefined binary printing in arm mode
+#skip: *-unknown-pe *-*-vxworks
+#source: undefined-insn.s
+#objdump: -D -b binary -m armv7e-m
+#...
--- /dev/null
+#name: Undefined binary printing in thumb mode
+#skip: *-unknown-pe *-*-vxworks
+#source: undefined-insn.s
+#objdump: -D -b binary -m armv7e-m -M force-thumb
+#...
--- /dev/null
+ .inst 0xffffffff
+2018-10-19 Tamar Christina <tamar.christina@arm.com>
+
+ * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
+ (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
+ (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
+
2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
} opcode_sentinels;
#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
+#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
+#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
return;
}
}
- abort ();
+ func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ return;
}
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
}
/* No match. */
- abort ();
+ func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
+ return;
}
/* Return the name of an V7M special register. */
}
/* No match. */
- abort ();
+ func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ return;
}
/* Print data bytes on INFO->STREAM. */