/*
* Never include sysdeps/powerpc/atomic-machine.h directly.
- * Alway use include/atomic.h which will include either
+ * Always use include/atomic.h which will include either
* sysdeps/powerpc/powerpc32/atomic-machine.h
* or
* sysdeps/powerpc/powerpc64/atomic-machine.h
/* The current powerpc 32-bit Altivec ABI specifies for SVR4 ABI and EABI
the vrsave must be at byte 248 & v20 at byte 256. So we must pad this
- correctly on 32 bit. It also insists that vecregs are only gauranteed
+ correctly on 32 bit. It also insists that vecregs are only guaranteed
4 byte alignment so we need to use vperm in the setjmp/longjmp routines.
We have to version the code because members like int __mask_was_saved
in the jmp_buf will move as jmp_buf is now larger than 248 bytes. We
r5:byte count
Save return address in r0.
- If destinationn and source are unaligned and copy count is greater than 256
+ If destination and source are unaligned and copy count is greater than 256
then copy 0-3 bytes to make destination aligned.
If 32 or more bytes to copy we use 32 byte copy loop.
- Finaly we copy 0-31 extra bytes. */
+ Finally we copy 0-31 extra bytes. */
EALIGN (memcpy, 5, 0)
/* Check if bytes to copy are greater than 256 and if
r12:temp return address
Save return address in r12
- If destinationn is unaligned and count is greater tha 255 bytes
+ If destination is unaligned and count is greater than 255 bytes
set 0-3 bytes to make destination aligned
- If count is greater tha 255 bytes and setting zero to memory
- use dbcz to set memeory when we can
- otherwsie do the follwoing
+ If count is greater than 255 bytes and setting zero to memory
+ use dbcz to set memory when we can
+ otherwise do the following
If 16 or more words to set we use 16 word copy loop.
- Finaly we set 0-15 extra bytes with string store. */
+ Finally we set 0-15 extra bytes with string store. */
EALIGN (memset, 5, 0)
rlwinm r11,r4,0,24,31
r12:temp return address
Save return address in r12
- If destinationn is unaligned and count is greater tha 255 bytes
+ If destination is unaligned and count is greater than 255 bytes
set 0-3 bytes to make destination aligned
- If count is greater tha 255 bytes and setting zero to memory
- use dbcz to set memeory when we can
- otherwsie do the follwoing
+ If count is greater than 255 bytes and setting zero to memory
+ use dbcz to set memory when we can
+ otherwise do the following
If 16 or more words to set we use 16 word copy loop.
- Finaly we set 0-15 extra bytes with string store. */
+ Finally we set 0-15 extra bytes with string store. */
EALIGN (memset, 5, 0)
rlwinm r11,r4,0,24,31
-/* Optimized strcasecmp_l implememtation for POWER7.
+/* Optimized strcasecmp_l implementation for POWER7.
Copyright (C) 2013-2023 Free Software Foundation, Inc.
This file is part of the GNU C Library.
-/* Optimized strcasecmp_l implememtation for POWER7.
+/* Optimized strcasecmp_l implementation for POWER7.
Copyright (C) 2013-2023 Free Software Foundation, Inc.
This file is part of the GNU C Library.
# We check if compiler supports @notoc generation since there is no
# gain by enabling it if it will be optimized away by the linker.
# It also helps linkers that might not optimize it and end up
-# generating stubs with ISA 3.1 instruction even targetting older ISA.
+# generating stubs with ISA 3.1 instruction even targeting older ISA.
AC_CACHE_CHECK([if the compiler supports @notoc],
libc_cv_ppc64_notoc, [dnl
cat > conftest.c <<EOF
Redirect func to a function named function ## variant ## reentrant_suffix
F128_REDIR(function)
- Convience wrapper for F128_REDIR_R where function does not require
+ Convenience wrapper for F128_REDIR_R where function does not require
a suffix argument.
*/
_F128_IFUNC2 (__ ## func ## f128, pfx2 ## func ## f128, r);
/* GEN_COMPAT_R_e(f)
- Generate a compatability symbol for finite alias of ieee function. */
+ Generate a compatibility symbol for finite alias of ieee function. */
#define GEN_COMPAT_R_e(f, r) \
libm_alias_finite (__ieee754_ ## f ## f128 ## r, __ ## f ## f128 ## r)
#include <float128-ifunc-macros.h>
-/* Declare these now. These prototyes are not included
+/* Declare these now. These prototypes are not included
in any header. */
extern __typeof (cosf128) __ieee754_cosf128;
extern __typeof (asinhf128) __ieee754_asinhf128;
/* Return original DST pointer. */
blr
- /* Start to memcpy backward implementation: the algorith first check if
+ /* Start to memcpy backward implementation: the algorithm first check if
src and dest have the same alignment and if it does align both to 16
bytes and copy using VSX instructions.
If does not, align dest to 16 bytes and use VMX (altivec) instruction
<https://www.gnu.org/licenses/>. */
/* The optimization is achieved here through cmpb instruction.
- 8byte aligned strings are processed with double word comparision
+ 8byte aligned strings are processed with double word comparison
and unaligned strings are handled effectively with loop unrolling
technique */
rldicl r6, r3, 0, 61 /* Recalculate padding */
mr r7, r6
- /* src is algined */
+ /* src is aligned */
L(srcaligndstunalign):
mr r9, r3
mr r6, r7
clrrdi r8,r3,3 /* Align the address to doubleword boundary. */
cmpdi cr7,r4,0
ld r12,0(r8) /* Load doubleword from memory. */
- li r9,0 /* used to store last occurence */
+ li r9,0 /* used to store last occurrence */
li r0,0 /* Doubleword with null chars to use
with cmpb. */
beq cr7, L(skipcheck)
cmpw cr7, r3, r29
ble cr7, L(firstpos)
- /* Move r3 to the first occurence. */
+ /* Move r3 to the first occurrence. */
L(skipcheck):
mr r3, r29
L(firstpos):
beq cr7, L(skipcheck1)
cmpw cr7, r3, r29
ble cr7, L(nextpos)
- /* Move r3 to first occurence. */
+ /* Move r3 to first occurrence. */
L(skipcheck1):
mr r3, r29
L(nextpos):
bdnz L(check_source2_byte_loop)
/* If source2 is unaligned to doubleword, the code needs to check
- on each interation if the unaligned doubleword access will cross
+ on each iteration if the unaligned doubleword access will cross
a 4k page boundary. */
.align 5
L(loop_unaligned):
L(align64):
/* Proceed to the old (POWER7) implementation, checking two doublewords
- per iteraction. For the first 56 bytes, we will just check for null
+ per iteration. For the first 56 bytes, we will just check for null
characters. After that, we will also check if we are 64-byte aligned
so we can jump to the vectorized implementation. We will unroll
these loops to avoid excessive branching. */
b L(loop_ne_align_1)
/* If source2 is unaligned to doubleword, the code needs to check
- on each interation if the unaligned doubleword access will cross
+ on each iteration if the unaligned doubleword access will cross
a 4k page boundary. */
.align 4
L(loop_ne_align_0):
.align 4
L(short_path_loop):
/* At this point, the induction variable, r5, as well as the pointers
- to dest and src (r9 and r4, respectivelly) have been updated.
+ to dest and src (r9 and r4, respectively) have been updated.
Note: The registers r7 and r10 are induction variables derived from
r5. They are used to determine if the total number of writes has
cmpdi cr7,r9,0
bne cr7,L(short_path_prepare_2)
- /* No null byte found in the 32 bytes readed and length not reached,
+ /* No null byte found in the 32 bytes read and length not reached,
read source again using unaligned loads and store them. */
ld r9,0(r4)
addi r29,r3,16
vminub v6,v3,v4
vminub v7,v5,v6
vcmpequb. v7,v7,v0 /* Check for null bytes. */
- addi r5,r5,64 /* Add pointer to next iteraction. */
+ addi r5,r5,64 /* Add pointer to next iteration. */
bne cr6,L(found_64B) /* If found null bytes. */
bdnz L(loop_64B) /* Continue the loop if count > 0. */
clrrdi r8,r3,3 /* Align the address to doubleword boundary. */
cmpdi cr7,r4,0
ld r12,0(r8) /* Load doubleword from memory. */
- li r9,0 /* Used to store last occurence. */
+ li r9,0 /* Used to store last occurrence. */
li r0,0 /* Doubleword with null chars to use
with cmpb. */
#include <string.h>
#include <setjmp.h>
-/* Copy r1 adress to a local variable. */
+/* Copy r1 address to a local variable. */
#define GET_STACK_POINTER(sp) \
({ \
asm volatile ("mr %0, 1\n\t" \
projects / platform / upstream / glibc.git / commitdiff