drm/komeda: fix 32-bit komeda_crtc_update_clock_ratio

clang points out a bug in the clock calculation on 32-bit, that leads
to the clock_ratio always being zero:

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c:31:36: error: shift count >= width of type [-Werror,-Wshift-count-overflow]
        aclk = komeda_calc_aclk(kcrtc_st) << 32;

Move the shift into the division to make it apply on a 64-bit
variable. Also use the more expensive div64_u64() instead of div_u64()
to account for pxlclk being a 64-bit integer.

Fixes: 1f7f9ab7900e ("drm/komeda: Add engine clock requirement check for the downscaling")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index cafb4457e187cfe8e88b0d7479ea62febf48292e..3f222f464eb2f2d15b37f52488cb8aadd0cea5f5 100644 (file)
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -28,10 +28,9 @@ static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st)
        }
 
        pxlclk = kcrtc_st->base.adjusted_mode.clock * 1000;
-       aclk = komeda_calc_aclk(kcrtc_st) << 32;
+       aclk = komeda_calc_aclk(kcrtc_st);
 
-       do_div(aclk, pxlclk);
-       kcrtc_st->clock_ratio = aclk;
+       kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk);
 }
 
 /**