Texture rectangle support for r100

diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index c0f1e75..912da0d 100644 (file)
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -141,7 +141,10 @@
 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
 #define R200_EMIT_PP_CUBIC_FACES_5                  71
 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
-#define RADEON_MAX_STATE_PACKETS                    73
+#define RADEON_EMIT_PP_TEX_SIZE_0                   73
+#define RADEON_EMIT_PP_TEX_SIZE_1                   74
+#define RADEON_EMIT_PP_TEX_SIZE_2                   75
+#define RADEON_MAX_STATE_PACKETS                    76
 
 
 /* Commands understood by cmd_buffer ioctl.  More can be added but

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 8b17b9d..6375647 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -669,6 +669,10 @@ extern void radeon_do_release(drm_device_t *dev);
 #define R200_RE_POINTSIZE                 0x2648
 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
 
+#define RADEON_PP_TEX_SIZE_0                0x1d04  /* NPOT */
+#define RADEON_PP_TEX_SIZE_1                0x1d0c
+#define RADEON_PP_TEX_SIZE_2                0x1d14
+
 
 #define SE_VAP_CNTL__TCL_ENA_MASK                          0x00000001
 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK                   0x00010000

diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 8e9485a..4dde9d2 100644 (file)
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -292,6 +292,9 @@ static struct {
        { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
        { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
        { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
+       { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
+       { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
+       { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
 };
 
 

diff --git a/shared/radeon.h b/shared/radeon.h
index d25adba..34386f3 100644 (file)
--- a/shared/radeon.h
+++ b/shared/radeon.h
@@ -51,7 +51,7 @@
 #define DRIVER_DATE            "20020828"
 
 #define DRIVER_MAJOR           1
-#define DRIVER_MINOR           8
+#define DRIVER_MINOR           9
 #define DRIVER_PATCHLEVEL      0
 
 /* Interface history:

diff --git a/shared/radeon_drm.h b/shared/radeon_drm.h
index c0f1e75..912da0d 100644 (file)
--- a/shared/radeon_drm.h
+++ b/shared/radeon_drm.h
@@ -141,7 +141,10 @@
 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
 #define R200_EMIT_PP_CUBIC_FACES_5                  71
 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
-#define RADEON_MAX_STATE_PACKETS                    73
+#define RADEON_EMIT_PP_TEX_SIZE_0                   73
+#define RADEON_EMIT_PP_TEX_SIZE_1                   74
+#define RADEON_EMIT_PP_TEX_SIZE_2                   75
+#define RADEON_MAX_STATE_PACKETS                    76
 
 
 /* Commands understood by cmd_buffer ioctl.  More can be added but

diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h
index 8b17b9d..6375647 100644 (file)
--- a/shared/radeon_drv.h
+++ b/shared/radeon_drv.h
@@ -669,6 +669,10 @@ extern void radeon_do_release(drm_device_t *dev);
 #define R200_RE_POINTSIZE                 0x2648
 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
 
+#define RADEON_PP_TEX_SIZE_0                0x1d04  /* NPOT */
+#define RADEON_PP_TEX_SIZE_1                0x1d0c
+#define RADEON_PP_TEX_SIZE_2                0x1d14
+
 
 #define SE_VAP_CNTL__TCL_ENA_MASK                          0x00000001
 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK                   0x00010000

diff --git a/shared/radeon_state.c b/shared/radeon_state.c
index 8e9485a..4dde9d2 100644 (file)
--- a/shared/radeon_state.c
+++ b/shared/radeon_state.c
@@ -292,6 +292,9 @@ static struct {
        { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
        { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
        { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
+       { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
+       { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
+       { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
 };