Increase the accuracy of sparc instruction aliases.

Make current with UA2011 specification.

Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.

For 'lzd':

	Add 'lzcnt' as primary instruction, and make 'lzd' an alias.

Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':

	The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
	integer registers.  Mark the latter now as aliases.

For 'flush':

	Support "[address]" syntax as well as plain "address".

Rework 'mov' aliases for 'wr':

	Eliminate bogus three operand moves, and encode the
	instructions properly for the "mov REG, %ASR" cases,
	specifically we should encode the register in rs2 not rs1 as
	per The SPARC V8 Architecture Manual.

Add missing cbcond aliases:

	c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu

Add 'd' suffix VIS logical ops:

	The primary opcode for 'fzero' is now 'fzerod' (compare with
	'fzeros'), for example.  And thus 'fzero' is now an alias.

Add modern opcodes for condition code setting edge instructions:

	They are now edgeN{,l}cc instead of plain edgeN{,l}.

Add modern opcodes for VIS comparisons:

	All VIS comparisons now start with prefix "fp", retain the
	older variants as aliases.

	The signed variants for equal and not-equal have "u" aliases
	to show that these comparisons are equally suited for unsigned
	compares.

Update existing test cases as needed, and add several new ones.

include/opcode/

	* sparc.h (F_PREFERRED): Define.
	(F_PREF_ALIAS): Define.

opcodes/

	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	of an opcode, prefer the one with F_PREFERRED set.
	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
	mark existing mnenomics as aliases.  Add "cc" suffix to edge
	instructions generating condition codes, mark existing mnenomics
	as aliases.  Add "fp" prefix to VIS compare instructions, mark
	existing mnenomics as aliases.

gas/testsuite/

	* gas/sparc/cbcond.s: Add tests for new opcode aliases.
	* gas/sparc/cbcond.d: Updated.
	* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
	* gas/sparc/hpcvis3.d: Updated.
	* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
	* gas/sparc/edge.s: New test.
	* gas/sparc/edge.d: Expected disassembly.
	* gas/sparc/flush.s: New test.
	* gas/sparc/flush.d: Expected disassembly.
	* gas/sparc/ldd_std.s: New test.
	* gas/sparc/ldd_std.d: Expected disassembly.
	* gas/sparc/ldtw_sttw.s: New test.
	* gas/sparc/ldtw_sttw.d: Expected disassembly.
	* gas/sparc/sparc.exp: Run new tests.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 7bd46f6..a4d193d 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2013-04-06  David S. Miller  <davem@davemloft.net>
+
+       * gas/sparc/cbcond.s: Add tests for new opcode aliases.
+       * gas/sparc/cbcond.d: Updated.
+       * gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
+       * gas/sparc/hpcvis3.d: Updated.
+       * gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
+       * gas/sparc/edge.s: New test.
+       * gas/sparc/edge.d: Expected disassembly.
+       * gas/sparc/flush.s: New test.
+       * gas/sparc/flush.d: Expected disassembly.
+       * gas/sparc/ldd_std.s: New test.
+       * gas/sparc/ldd_std.d: Expected disassembly.
+       * gas/sparc/ldtw_sttw.s: New test.
+       * gas/sparc/ldtw_sttw.d: Expected disassembly.
+       * gas/sparc/sparc.exp: Run new tests.
+
 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 
        PR binutils/15068

diff --git a/gas/testsuite/gas/sparc/cbcond.d b/gas/testsuite/gas/sparc/cbcond.d
index d094045..3f5b5b2 100644 (file)
--- a/gas/testsuite/gas/sparc/cbcond.d
+++ b/gas/testsuite/gas/sparc/cbcond.d
@@ -7,60 +7,76 @@
 Disassembly of section .text:
 
 0+ <.text>:
-   0:  12 c2 47 0a     cwbe  %o1, %o2, 0xe0
-   4:  12 c2 66 e2     cwbe  %o1, 2, 0xe0
-   8:  12 e2 86 cb     cxbe  %o2, %o3, 0xe0
-   c:  12 e2 a6 a3     cxbe  %o2, 3, 0xe0
-  10:  14 c2 c6 8c     cwble  %o3, %o4, 0xe0
-  14:  14 c2 e6 64     cwble  %o3, 4, 0xe0
-  18:  14 e3 06 4d     cxble  %o4, %o5, 0xe0
-  1c:  14 e3 26 25     cxble  %o4, 5, 0xe0
-  20:  16 c3 46 10     cwbl  %o5, %l0, 0xe0
-  24:  16 c3 65 e6     cwbl  %o5, 6, 0xe0
-  28:  16 e4 05 d1     cxbl  %l0, %l1, 0xe0
-  2c:  16 e4 25 a7     cxbl  %l0, 7, 0xe0
-  30:  18 c4 45 92     cwbleu  %l1, %l2, 0xe0
-  34:  18 c4 65 68     cwbleu  %l1, 8, 0xe0
-  38:  18 e4 85 53     cxbleu  %l2, %l3, 0xe0
-  3c:  18 e4 a5 29     cxbleu  %l2, 9, 0xe0
-  40:  1a c4 c5 14     cwbcs  %l3, %l4, 0xe0
-  44:  1a c4 e4 ea     cwbcs  %l3, 0xa, 0xe0
-  48:  1a e5 04 d5     cxbcs  %l4, %l5, 0xe0
-  4c:  1a e5 24 ab     cxbcs  %l4, 0xb, 0xe0
-  50:  1c c5 44 96     cwbneg  %l5, %l6, 0xe0
-  54:  1c c5 64 6c     cwbneg  %l5, 0xc, 0xe0
-  58:  1c e5 84 57     cxbneg  %l6, %l7, 0xe0
-  5c:  1c e5 a4 2d     cxbneg  %l6, 0xd, 0xe0
-  60:  1e c5 c4 18     cwbvs  %l7, %i0, 0xe0
-  64:  1e c5 e3 ee     cwbvs  %l7, 0xe, 0xe0
-  68:  1e e6 03 d9     cxbvs  %i0, %i1, 0xe0
-  6c:  1e e6 23 af     cxbvs  %i0, 0xf, 0xe0
-  70:  32 c6 43 9a     cwbne  %i1, %i2, 0xe0
-  74:  32 c6 63 70     cwbne  %i1, 0x10, 0xe0
-  78:  32 e6 83 5b     cxbne  %i2, %i3, 0xe0
-  7c:  32 e6 a3 31     cxbne  %i2, 0x11, 0xe0
-  80:  34 c6 c3 1c     cwbg  %i3, %i4, 0xe0
-  84:  34 c6 e2 f2     cwbg  %i3, 0x12, 0xe0
-  88:  34 e7 02 dd     cxbg  %i4, %i5, 0xe0
-  8c:  34 e7 22 b3     cxbg  %i4, 0x13, 0xe0
-  90:  36 c7 42 88     cwbge  %i5, %o0, 0xe0
-  94:  36 c7 62 74     cwbge  %i5, 0x14, 0xe0
-  98:  36 e2 02 49     cxbge  %o0, %o1, 0xe0
-  9c:  36 e2 22 35     cxbge  %o0, 0x15, 0xe0
-  a0:  38 c2 42 0a     cwbgu  %o1, %o2, 0xe0
-  a4:  38 c2 61 f6     cwbgu  %o1, 0x16, 0xe0
-  a8:  38 e2 81 cb     cxbgu  %o2, %o3, 0xe0
-  ac:  38 e2 a1 b6     cxbgu  %o2, 0x16, 0xe0
-  b0:  3a c2 c1 8c     cwbcc  %o3, %o4, 0xe0
-  b4:  3a c2 e1 77     cwbcc  %o3, 0x17, 0xe0
-  b8:  3a e3 01 4d     cxbcc  %o4, %o5, 0xe0
-  bc:  3a e3 21 38     cxbcc  %o4, 0x18, 0xe0
-  c0:  3c c3 41 10     cwbpos  %o5, %l0, 0xe0
-  c4:  3c c3 60 f9     cwbpos  %o5, 0x19, 0xe0
-  c8:  3c e4 00 d1     cxbpos  %l0, %l1, 0xe0
-  cc:  3c e4 20 b9     cxbpos  %l0, 0x19, 0xe0
-  d0:  3e c4 40 92     cwbvc  %l1, %l2, 0xe0
-  d4:  3e c4 60 7a     cwbvc  %l1, 0x1a, 0xe0
-  d8:  3e e4 80 53     cxbvc  %l2, %l3, 0xe0
-  dc:  3e e4 a0 3b     cxbvc  %l2, 0x1b, 0xe0
-  e0:  01 00 00 00     nop 
+   0:  12 c2 49 0a     cwbe  %o1, %o2, 0x120
+   4:  12 c2 68 e2     cwbe  %o1, 2, 0x120
+   8:  12 e2 88 cb     cxbe  %o2, %o3, 0x120
+   c:  12 e2 a8 a3     cxbe  %o2, 3, 0x120
+  10:  14 c2 c8 8c     cwble  %o3, %o4, 0x120
+  14:  14 c2 e8 64     cwble  %o3, 4, 0x120
+  18:  14 e3 08 4d     cxble  %o4, %o5, 0x120
+  1c:  14 e3 28 25     cxble  %o4, 5, 0x120
+  20:  16 c3 48 10     cwbl  %o5, %l0, 0x120
+  24:  16 c3 67 e6     cwbl  %o5, 6, 0x120
+  28:  16 e4 07 d1     cxbl  %l0, %l1, 0x120
+  2c:  16 e4 27 a7     cxbl  %l0, 7, 0x120
+  30:  18 c4 47 92     cwbleu  %l1, %l2, 0x120
+  34:  18 c4 67 68     cwbleu  %l1, 8, 0x120
+  38:  18 e4 87 53     cxbleu  %l2, %l3, 0x120
+  3c:  18 e4 a7 29     cxbleu  %l2, 9, 0x120
+  40:  1a c4 c7 14     cwbcs  %l3, %l4, 0x120
+  44:  1a c4 e6 ea     cwbcs  %l3, 0xa, 0x120
+  48:  1a e5 06 d5     cxbcs  %l4, %l5, 0x120
+  4c:  1a e5 26 ab     cxbcs  %l4, 0xb, 0x120
+  50:  1c c5 46 96     cwbneg  %l5, %l6, 0x120
+  54:  1c c5 66 6c     cwbneg  %l5, 0xc, 0x120
+  58:  1c e5 86 57     cxbneg  %l6, %l7, 0x120
+  5c:  1c e5 a6 2d     cxbneg  %l6, 0xd, 0x120
+  60:  1e c5 c6 18     cwbvs  %l7, %i0, 0x120
+  64:  1e c5 e5 ee     cwbvs  %l7, 0xe, 0x120
+  68:  1e e6 05 d9     cxbvs  %i0, %i1, 0x120
+  6c:  1e e6 25 af     cxbvs  %i0, 0xf, 0x120
+  70:  32 c6 45 9a     cwbne  %i1, %i2, 0x120
+  74:  32 c6 65 70     cwbne  %i1, 0x10, 0x120
+  78:  32 e6 85 5b     cxbne  %i2, %i3, 0x120
+  7c:  32 e6 a5 31     cxbne  %i2, 0x11, 0x120
+  80:  34 c6 c5 1c     cwbg  %i3, %i4, 0x120
+  84:  34 c6 e4 f2     cwbg  %i3, 0x12, 0x120
+  88:  34 e7 04 dd     cxbg  %i4, %i5, 0x120
+  8c:  34 e7 24 b3     cxbg  %i4, 0x13, 0x120
+  90:  36 c7 44 88     cwbge  %i5, %o0, 0x120
+  94:  36 c7 64 74     cwbge  %i5, 0x14, 0x120
+  98:  36 e2 04 49     cxbge  %o0, %o1, 0x120
+  9c:  36 e2 24 35     cxbge  %o0, 0x15, 0x120
+  a0:  38 c2 44 0a     cwbgu  %o1, %o2, 0x120
+  a4:  38 c2 63 f6     cwbgu  %o1, 0x16, 0x120
+  a8:  38 e2 83 cb     cxbgu  %o2, %o3, 0x120
+  ac:  38 e2 a3 b6     cxbgu  %o2, 0x16, 0x120
+  b0:  3a c2 c3 8c     cwbcc  %o3, %o4, 0x120
+  b4:  3a c2 e3 77     cwbcc  %o3, 0x17, 0x120
+  b8:  3a e3 03 4d     cxbcc  %o4, %o5, 0x120
+  bc:  3a e3 23 38     cxbcc  %o4, 0x18, 0x120
+  c0:  3c c3 43 10     cwbpos  %o5, %l0, 0x120
+  c4:  3c c3 62 f9     cwbpos  %o5, 0x19, 0x120
+  c8:  3c e4 02 d1     cxbpos  %l0, %l1, 0x120
+  cc:  3c e4 22 b9     cxbpos  %l0, 0x19, 0x120
+  d0:  3e c4 42 92     cwbvc  %l1, %l2, 0x120
+  d4:  3e c4 62 7a     cwbvc  %l1, 0x1a, 0x120
+  d8:  3e e4 82 53     cxbvc  %l2, %l3, 0x120
+  dc:  3e e4 a2 3b     cxbvc  %l2, 0x1b, 0x120
+  e0:  12 c4 c2 14     cwbe  %l3, %l4, 0x120
+  e4:  12 c4 e1 fc     cwbe  %l3, 0x1c, 0x120
+  e8:  12 e5 01 d5     cxbe  %l4, %l5, 0x120
+  ec:  12 e5 21 bd     cxbe  %l4, 0x1d, 0x120
+  f0:  1a c5 41 96     cwbcs  %l5, %l6, 0x120
+  f4:  1a c5 61 7c     cwbcs  %l5, 0x1c, 0x120
+  f8:  1a e5 81 57     cxbcs  %l6, %l7, 0x120
+  fc:  1a e5 a1 3d     cxbcs  %l6, 0x1d, 0x120
+ 100:  32 c5 c1 08     cwbne  %l7, %o0, 0x120
+ 104:  32 c5 e0 fe     cwbne  %l7, 0x1e, 0x120
+ 108:  32 e2 00 c9     cxbne  %o0, %o1, 0x120
+ 10c:  32 e2 20 bf     cxbne  %o0, 0x1f, 0x120
+ 110:  3a c2 40 8a     cwbcc  %o1, %o2, 0x120
+ 114:  3a c2 60 61     cwbcc  %o1, 1, 0x120
+ 118:  3a e2 80 4b     cxbcc  %o2, %o3, 0x120
+ 11c:  3a e2 a0 22     cxbcc  %o2, 2, 0x120
+ 120:  01 00 00 00     nop 

diff --git a/gas/testsuite/gas/sparc/cbcond.s b/gas/testsuite/gas/sparc/cbcond.s
index 2d15243..a538599 100644 (file)
--- a/gas/testsuite/gas/sparc/cbcond.s
+++ b/gas/testsuite/gas/sparc/cbcond.s
@@ -56,4 +56,20 @@
        cwbvc   %l1, 26, 1f
        cxbvc   %l2, %l3, 1f
        cxbvc   %l2, 27, 1f
+       cwbz    %l3, %l4, 1f
+       cwbz    %l3, 28, 1f
+       cxbz    %l4, %l5, 1f
+       cxbz    %l4, 29, 1f
+       cwblu   %l5, %l6, 1f
+       cwblu   %l5, 28, 1f
+       cxblu   %l6, %l7, 1f
+       cxblu   %l6, 29, 1f
+       cwbnz   %l7, %o0, 1f
+       cwbnz   %l7, 30, 1f
+       cxbnz   %o0, %o1, 1f
+       cxbnz   %o0, 31, 1f
+       cwbgeu  %o1, %o2, 1f
+       cwbgeu  %o1, 1, 1f
+       cxbgeu  %o2, %o3, 1f
+       cxbgeu  %o2, 2, 1f
 1:     nop

diff --git a/gas/testsuite/gas/sparc/edge.d b/gas/testsuite/gas/sparc/edge.d
new file mode 100644 (file)
index 0000000..340eee0
--- /dev/null
+++ b/gas/testsuite/gas/sparc/edge.d
@@ -0,0 +1,27 @@
+#as: -Av9d
+#objdump: -dr
+#name: sparc EDGE
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  87 b0 40 02     edge8cc  %g1, %g2, %g3
+   4:  87 b0 40 02     edge8cc  %g1, %g2, %g3
+   8:  87 b0 40 22     edge8n  %g1, %g2, %g3
+   c:  89 b0 80 43     edge8lcc  %g2, %g3, %g4
+  10:  89 b0 80 43     edge8lcc  %g2, %g3, %g4
+  14:  89 b0 80 63     edge8ln  %g2, %g3, %g4
+  18:  83 b5 00 02     edge8cc  %l4, %g2, %g1
+  1c:  83 b5 00 02     edge8cc  %l4, %g2, %g1
+  20:  83 b5 00 22     edge8n  %l4, %g2, %g1
+  24:  a9 b0 80 41     edge8lcc  %g2, %g1, %l4
+  28:  a9 b0 80 41     edge8lcc  %g2, %g1, %l4
+  2c:  a9 b0 80 61     edge8ln  %g2, %g1, %l4
+  30:  95 b3 41 0c     edge32cc  %o5, %o4, %o2
+  34:  95 b3 41 0c     edge32cc  %o5, %o4, %o2
+  38:  95 b3 41 2c     edge32n  %o5, %o4, %o2
+  3c:  a3 b2 81 45     edge32lcc  %o2, %g5, %l1
+  40:  a3 b2 81 45     edge32lcc  %o2, %g5, %l1
+  44:  a3 b2 81 65     edge32ln  %o2, %g5, %l1

diff --git a/gas/testsuite/gas/sparc/edge.s b/gas/testsuite/gas/sparc/edge.s
new file mode 100644 (file)
index 0000000..ce99cfd
--- /dev/null
+++ b/gas/testsuite/gas/sparc/edge.s
@@ -0,0 +1,20 @@
+# Test VIS EDGE instructions
+       .text
+       edge8cc         %g1, %g2, %g3
+       edge8           %g1, %g2, %g3
+       edge8n          %g1, %g2, %g3
+       edge8lcc        %g2, %g3, %g4
+       edge8l          %g2, %g3, %g4
+       edge8ln         %g2, %g3, %g4
+       edge8cc         %l4, %g2, %g1
+       edge8           %l4, %g2, %g1
+       edge8n          %l4, %g2, %g1
+       edge8lcc        %g2, %g1, %l4
+       edge8l          %g2, %g1, %l4
+       edge8ln         %g2, %g1, %l4
+       edge32cc        %o5, %o4, %o2
+       edge32          %o5, %o4, %o2
+       edge32n         %o5, %o4, %o2
+       edge32lcc       %o2, %g5, %l1
+       edge32l         %o2, %g5, %l1
+       edge32ln        %o2, %g5, %l1

diff --git a/gas/testsuite/gas/sparc/flush.d b/gas/testsuite/gas/sparc/flush.d
new file mode 100644 (file)
index 0000000..d82ed2a
--- /dev/null
+++ b/gas/testsuite/gas/sparc/flush.d
@@ -0,0 +1,17 @@
+#as: -Av9
+#objdump: -dr
+#name: sparc FLUSH
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  81 d8 40 02     flush  \[ %g1 \+ %g2 \]
+   4:  81 d8 40 02     flush  \[ %g1 \+ %g2 \]
+   8:  81 d8 c0 00     flush  \[ %g3 \]
+   c:  81 d8 c0 00     flush  \[ %g3 \]
+  10:  81 d9 20 80     flush  \[ %g4 \+ 0x80 \]
+  14:  81 d9 20 80     flush  \[ %g4 \+ 0x80 \]
+  18:  81 d9 60 90     flush  \[ %g5 \+ 0x90 \]
+  1c:  81 d9 60 90     flush  \[ %g5 \+ 0x90 \]

diff --git a/gas/testsuite/gas/sparc/flush.s b/gas/testsuite/gas/sparc/flush.s
new file mode 100644 (file)
index 0000000..06cae0f
--- /dev/null
+++ b/gas/testsuite/gas/sparc/flush.s
@@ -0,0 +1,10 @@
+# Test FLUSH instruction
+       .text
+       flush   [%g1 + %g2]
+       flush   %g1 + %g2
+       flush   [%g3]
+       flush   %g3
+       flush   [%g4 + 0x80]
+       flush   %g4 + 0x80
+       flush   [0x90 + %g5]
+       flush   0x90 + %g5

diff --git a/gas/testsuite/gas/sparc/hpcvis3.d b/gas/testsuite/gas/sparc/hpcvis3.d
index f4606ac..8b920a5 100644 (file)
--- a/gas/testsuite/gas/sparc/hpcvis3.d
+++ b/gas/testsuite/gas/sparc/hpcvis3.d
@@ -43,7 +43,7 @@ Disassembly of section .text:
   84:  97 b2 42 6a     addxccc  %o1, %o2, %o3
   88:  8d b0 02 a0     random  %f6
   8c:  9f b3 42 ce     umulxhi  %o5, %sp, %o7
-  90:  b5 b0 02 f9     lzd  %i1, %i2
+  90:  b5 b0 02 f9     lzcnt  %i1, %i2
   94:  81 b0 03 7b     cmask8  %i3
   98:  81 b0 03 bc     cmask16  %i4
   9c:  81 b0 03 fd     cmask32  %i5
@@ -75,10 +75,10 @@ Disassembly of section .text:
  104:  af b0 23 25     movwtos  %g5, %f23
  108:  97 b2 62 aa     xmulx  %o1, %o2, %o3
  10c:  9d b3 22 cd     xmulxhi  %o4, %o5, %sp
- 110:  83 b4 24 12     fucmple8  %f16, %f18, %g1
- 114:  85 b4 a4 54     fucmpne8  %f18, %f20, %g2
- 118:  87 b5 25 16     fucmpgt8  %f20, %f22, %g3
- 11c:  89 b5 a5 58     fucmpeq8  %f22, %f24, %g4
+ 110:  83 b4 24 12     fpcmpule8  %f16, %f18, %g1
+ 114:  85 b4 a4 54     fpcmpune8  %f18, %f20, %g2
+ 118:  87 b5 25 16     fpcmpugt8  %f20, %f22, %g3
+ 11c:  89 b5 a5 58     fpcmpueq8  %f22, %f24, %g4
  120:  81 b0 6a 23     flcmps  %fcc0, %f1, %f3
  124:  83 b0 ea 25     flcmps  %fcc1, %f3, %f5
  128:  85 b1 6a 27     flcmps  %fcc2, %f5, %f7
@@ -87,3 +87,4 @@ Disassembly of section .text:
  134:  83 b3 aa 50     flcmpd  %fcc1, %f14, %f16
  138:  85 b4 2a 52     flcmpd  %fcc2, %f16, %f18
  13c:  87 b4 aa 54     flcmpd  %fcc3, %f18, %f20
+ 140:  b5 b0 02 f9     lzcnt  %i1, %i2

diff --git a/gas/testsuite/gas/sparc/hpcvis3.s b/gas/testsuite/gas/sparc/hpcvis3.s
index 9f3ac36..e960557 100644 (file)
--- a/gas/testsuite/gas/sparc/hpcvis3.s
+++ b/gas/testsuite/gas/sparc/hpcvis3.s
@@ -36,7 +36,7 @@
        addxccc %o1, %o2, %o3
        random  %f6
        umulxhi %o5, %o6, %o7
-       lzd     %i1, %i2
+       lzcnt   %i1, %i2
        cmask8  %i3
        cmask16 %i4
        cmask32 %i5
@@ -80,3 +80,4 @@
        flcmpd  %fcc1, %f14, %f16
        flcmpd  %fcc2, %f16, %f18
        flcmpd  %fcc3, %f18, %f20
+       lzd     %i1, %i2

diff --git a/gas/testsuite/gas/sparc/ldd_std.d b/gas/testsuite/gas/sparc/ldd_std.d
new file mode 100644 (file)
index 0000000..2d0083b
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldd_std.d
@@ -0,0 +1,13 @@
+#as: -Av8
+#objdump: -dr
+#name: sparc LDD/STD
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  d0 18 c0 00     ldd  \[ %g3 \], %o0
+   4:  d4 98 c0 80     ldda  \[ %g3 \] #ASI_N, %o2
+   8:  d0 38 c0 00     std  %o0, \[ %g3 \]
+   c:  d4 b8 c0 80     stda  %o2, \[ %g3 \] #ASI_N

diff --git a/gas/testsuite/gas/sparc/ldd_std.s b/gas/testsuite/gas/sparc/ldd_std.s
new file mode 100644 (file)
index 0000000..5c08055
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldd_std.s
@@ -0,0 +1,6 @@
+# Test ldd/ldda/std/stda
+       .text
+       ldd     [%g3], %o0
+       ldda    [%g3] 0x04, %o2
+       std     %o0, [%g3]
+       stda    %o2, [%g3] 0x04

diff --git a/gas/testsuite/gas/sparc/ldtw_sttw.d b/gas/testsuite/gas/sparc/ldtw_sttw.d
new file mode 100644 (file)
index 0000000..084c1e3
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldtw_sttw.d
@@ -0,0 +1,15 @@
+#as: -Av9
+#objdump: -dr
+#name: sparc LDTW/STTW
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  d0 18 c0 00     ldtw  \[ %g3 \], %o0
+   4:  d4 98 c0 80     ldtwa  \[ %g3 \] #ASI_N, %o2
+   8:  d8 98 e0 00     ldtwa  \[ %g3 \] %asi, %o4
+   c:  d0 38 c0 00     sttw  %o0, \[ %g3 \]
+  10:  d4 b8 c0 80     sttwa  %o2, \[ %g3 \] #ASI_N
+  14:  d8 b8 e0 00     sttwa  %o4, \[ %g3 \] %asi

diff --git a/gas/testsuite/gas/sparc/ldtw_sttw.s b/gas/testsuite/gas/sparc/ldtw_sttw.s
new file mode 100644 (file)
index 0000000..23d5a2e
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldtw_sttw.s
@@ -0,0 +1,8 @@
+# Test ldtw/ldtwa/sttw/sttwa
+       .text
+       ldtw    [%g3], %o0
+       ldtwa   [%g3] 0x04, %o2
+       ldtwa   [%g3] %asi, %o4
+       sttw    %o0, [%g3]
+       sttwa   %o2, [%g3] 0x04
+       sttwa   %o4, [%g3] %asi

diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index 8326d80..28d8a4f 100644 (file)
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -83,6 +83,10 @@ if [istarget sparc*-*-*] {
     run_dump_test "cbcond"
     run_dump_test "pause"
     run_dump_test "cfr"
+    run_dump_test "ldtw_sttw"
+    run_dump_test "ldd_std"
+    run_dump_test "edge"
+    run_dump_test "flush"
 
     run_list_test "pr4587" ""
 }

diff --git a/gas/testsuite/gas/sparc/v8-movwr-imm.d b/gas/testsuite/gas/sparc/v8-movwr-imm.d
index e0c1a00..5988d4d 100644 (file)
--- a/gas/testsuite/gas/sparc/v8-movwr-imm.d
+++ b/gas/testsuite/gas/sparc/v8-movwr-imm.d
@@ -7,43 +7,43 @@
 Disassembly of section .text:
 
 0+ <foo>:
-   0:  83 80 00 10     mov  %l0, %asr1
-   4:  81 80 00 10     mov  %l0, %y
-   8:  81 88 00 10     mov  %l0, %psr
-   c:  81 90 00 10     mov  %l0, %wim
-  10:  81 98 00 10     mov  %l0, %tbr
-  14:  83 80 00 00     mov  %g0, %asr1
-  18:  81 80 00 00     mov  %g0, %y
-  1c:  81 88 00 00     mov  %g0, %psr
-  20:  81 90 00 00     mov  %g0, %wim
-  24:  81 98 00 00     mov  %g0, %tbr
-  28:  83 80 20 00     mov  %g0, %asr1
-  2c:  81 80 20 00     mov  %g0, %y
-  30:  81 88 20 00     mov  %g0, %psr
-  34:  81 90 20 00     mov  %g0, %wim
-  38:  81 98 20 00     mov  %g0, %tbr
-  3c:  83 80 3f ff     mov  -1, %asr1
-  40:  81 80 3f ff     mov  -1, %y
-  44:  81 88 3f ff     mov  -1, %psr
-  48:  81 90 3f ff     mov  -1, %wim
-  4c:  81 98 3f ff     mov  -1, %tbr
-  50:  83 80 00 10     mov  %l0, %asr1
-  54:  81 80 00 10     mov  %l0, %y
-  58:  81 88 00 10     mov  %l0, %psr
-  5c:  81 90 00 10     mov  %l0, %wim
-  60:  81 98 00 10     mov  %l0, %tbr
-  64:  83 80 00 00     mov  %g0, %asr1
-  68:  81 80 00 00     mov  %g0, %y
-  6c:  81 88 00 00     mov  %g0, %psr
-  70:  81 90 00 00     mov  %g0, %wim
-  74:  81 98 00 00     mov  %g0, %tbr
-  78:  83 80 20 00     mov  %g0, %asr1
-  7c:  81 80 20 00     mov  %g0, %y
-  80:  81 88 20 00     mov  %g0, %psr
-  84:  81 90 20 00     mov  %g0, %wim
-  88:  81 98 20 00     mov  %g0, %tbr
-  8c:  83 80 3f ff     mov  -1, %asr1
-  90:  81 80 3f ff     mov  -1, %y
-  94:  81 88 3f ff     mov  -1, %psr
-  98:  81 90 3f ff     mov  -1, %wim
-  9c:  81 98 3f ff     mov  -1, %tbr
+   0:  83 80 00 10     wr  %l0, %asr1
+   4:  81 80 00 10     wr  %l0, %y
+   8:  81 88 00 10     wr  %l0, %psr
+   c:  81 90 00 10     wr  %l0, %wim
+  10:  81 98 00 10     wr  %l0, %tbr
+  14:  83 80 00 00     wr  %g0, %asr1
+  18:  81 80 00 00     wr  %g0, %y
+  1c:  81 88 00 00     wr  %g0, %psr
+  20:  81 90 00 00     wr  %g0, %wim
+  24:  81 98 00 00     wr  %g0, %tbr
+  28:  83 80 20 00     wr  %g0, %asr1
+  2c:  81 80 20 00     wr  %g0, %y
+  30:  81 88 20 00     wr  %g0, %psr
+  34:  81 90 20 00     wr  %g0, %wim
+  38:  81 98 20 00     wr  %g0, %tbr
+  3c:  83 80 3f ff     wr  -1, %asr1
+  40:  81 80 3f ff     wr  -1, %y
+  44:  81 88 3f ff     wr  -1, %psr
+  48:  81 90 3f ff     wr  -1, %wim
+  4c:  81 98 3f ff     wr  -1, %tbr
+  50:  83 80 00 10     wr  %l0, %asr1
+  54:  81 80 00 10     wr  %l0, %y
+  58:  81 88 00 10     wr  %l0, %psr
+  5c:  81 90 00 10     wr  %l0, %wim
+  60:  81 98 00 10     wr  %l0, %tbr
+  64:  83 80 00 00     wr  %g0, %asr1
+  68:  81 80 00 00     wr  %g0, %y
+  6c:  81 88 00 00     wr  %g0, %psr
+  70:  81 90 00 00     wr  %g0, %wim
+  74:  81 98 00 00     wr  %g0, %tbr
+  78:  83 80 20 00     wr  %g0, %asr1
+  7c:  81 80 20 00     wr  %g0, %y
+  80:  81 88 20 00     wr  %g0, %psr
+  84:  81 90 20 00     wr  %g0, %wim
+  88:  81 98 20 00     wr  %g0, %tbr
+  8c:  83 80 3f ff     wr  -1, %asr1
+  90:  81 80 3f ff     wr  -1, %y
+  94:  81 88 3f ff     wr  -1, %psr
+  98:  81 90 3f ff     wr  -1, %wim
+  9c:  81 98 3f ff     wr  -1, %tbr

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index cf53c8c..9eed104 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2013-04-06  David S. Miller  <davem@davemloft.net>
+
+       * sparc.h (F_PREFERRED): Define.
+       (F_PREF_ALIAS): Define.
+
 2013-04-03  Nick Clifton  <nickc@redhat.com>
 
        * v850.h (V850_INVERSE_PCREL): Define.

diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 8927769..f2799b7 100644 (file)
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -111,6 +111,9 @@ typedef struct sparc_opcode
 #define        F_JSR           0x00000010 /* Subroutine call.  */
 #define F_FLOAT                0x00000020 /* Floating point instruction (not a branch).  */
 #define F_FBR          0x00000040 /* Floating point branch.  */
+#define F_PREFERRED    0x00000080 /* A preferred alias.  */
+
+#define F_PREF_ALIAS   (F_ALIAS|F_PREFERRED)
 
 /* These must match the HWCAP_* values precisely.  */
 #define HWCAP_MUL32    0x00000001 /* umul/umulcc/smul/smulcc insns */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dfd3969..c3eb918 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2013-04-06  David S. Miller  <davem@davemloft.net>
+
+       * sparc-dis.c (compare_opcodes): When encountering multiple aliases
+       of an opcode, prefer the one with F_PREFERRED set.
+       * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
+       lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
+       ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
+       mark existing mnenomics as aliases.  Add "cc" suffix to edge
+       instructions generating condition codes, mark existing mnenomics
+       as aliases.  Add "fp" prefix to VIS compare instructions, mark
+       existing mnenomics as aliases.
+
 2013-04-03  Nick Clifton  <nickc@redhat.com>
 
        * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the

diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index f0ee518..fcbf89d 100644 (file)
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -338,8 +338,17 @@ compare_opcodes (const void * a, const void * b)
   i = strcmp (op0->name, op1->name);
   if (i)
     {
-      if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary.  */
-       return i;
+      if (op0->flags & F_ALIAS)
+       {
+         if (op0->flags & F_PREFERRED)
+           return -1;
+         if (op1->flags & F_PREFERRED)
+           return 1;
+
+         /* If they're both aliases, and neither is marked as preferred,
+            be arbitrary.  */
+         return i;
+       }
       else
        fprintf (stderr,
                 /* xgettext:c-format */

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 87634ae..a0d0be2 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -219,18 +219,25 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", F_ALIAS, 0, v9 },
 { "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
 
-{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", 0, 0, v6 },
-{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v6 }, /* ldd [rs1+%g0],d */
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, 0, v6 },
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, 0, v6 },
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, 0, v6 },
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", 0, 0, v6 }, /* ldd [rs1+0],d */
-{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),      "[1+2],H", 0, 0, v6 },
-{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", 0, 0, v6 }, /* ldd [rs1+%g0],d */
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", 0, 0, v6 },
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", 0, 0, v6 },
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", 0, 0, v6 },
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),   "[1],H", 0, 0, v6 }, /* ldd [rs1+0],d */
+{ "ldtw",      F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v9 }, /* ldd [rs1+%g0],d */
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", 0, 0, v9 }, /* ldd [rs1+0],d */
+
+{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", F_ALIAS, 0, v6 }, /* ldd [rs1+%g0],d */
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, 0, v6 }, /* ldd [rs1+0],d */
+{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),      "[1+2],H", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", F_ALIAS, 0, v6 }, /* ldd [rs1+%g0],d */
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", F_ALIAS, 0, v6 },
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),   "[1],H", F_ALIAS, 0, v6 }, /* ldd [rs1+0],d */
 
 { "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),      "[1+2],D", 0, 0, v6notv9 },
 { "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),  "[1],D", 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */
@@ -322,12 +329,19 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i]o,g", 0, 0, v9 },
 { "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1]o,g", 0, 0, v9 }, /* ld [rs1+0],d */
 
-{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", 0, 0, v6 },
-{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", 0, 0, v6 }, /* ldda [rs1+%g0],d */
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
+{ "ldtwa",     F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", 0, 0, v9 }, /* ldda [rs1+%g0],d */
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", F_ALIAS, 0, v6 },
+{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", F_ALIAS, 0, v6 }, /* ldda [rs1+%g0],d */
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", F_ALIAS, 0, v9 },
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", F_ALIAS, 0, v9 },
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", F_ALIAS, 0, v9 },
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
 
 { "ldda",      F3(3, 0x33, 0), F3(~3, ~0x33, ~0),              "[1+2]A,H", 0, 0, v9 },
 { "ldda",      F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0,       "[1]A,H", 0, 0, v9 }, /* ldda [rs1+%g0],d */
@@ -531,12 +545,19 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
 { "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */
 
-{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", 0, 0, v6 },
-{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, v6 }, /* std d,[rs1+%g0] */
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", 0, 0, v6 },
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", 0, 0, v6 },
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", 0, 0, v6 },
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", 0, 0, v6 }, /* std d,[rs1+0] */
+{ "sttw",      F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, v9 }, /* std d,[rs1+%g0] */
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", 0, 0, v9 }, /* std d,[rs1+0] */
+
+{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", F_PREF_ALIAS, 0, v6 },
+{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_PREF_ALIAS, 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", F_PREF_ALIAS, 0, v6 },
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", F_PREF_ALIAS, 0, v6 },
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_PREF_ALIAS, 0, v6 },
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", F_PREF_ALIAS, 0, v6 }, /* std d,[rs1+0] */
 
 { "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "q,[1+2]", 0, 0, v6notv9 },
 { "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
@@ -571,12 +592,19 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v6 },
 { "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+0] */
 
-{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", 0, 0, v6 },
-{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", 0, 0, v6 }, /* stda d,[rs1+%g0] */
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", 0, 0, v9 },
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", 0, 0, v9 },
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", 0, 0, v9 },
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
+{ "sttwa",     F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
+
+{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", F_ALIAS, 0, v6 },
+{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v6 }, /* stda d,[rs1+%g0] */
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* std d,[rs1+0] */
 { "stda",      F3(3, 0x37, 0), F3(~3, ~0x37, ~0),              "H,[1+2]A", 0, 0, v9 },
 { "stda",      F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0),      "H,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */
 { "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[1+i]o", 0, 0, v9 },
@@ -711,12 +739,19 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "invalw",    F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
 { "sir",       F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,              "i", 0, 0, v9 },
 
-{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", 0, 0, v8 },
-{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", 0, 0, v8 }, /* flush rs1+%g0 */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", 0, 0, v8 }, /* flush rs1+0 */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", 0, 0, v8 }, /* flush %g0+i */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", 0, 0, v8 },
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", 0, 0, v8 },
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "[1+2]", 0, 0, v9 },
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "[1]", 0, 0, v9 }, /* flush rs1+%g0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "[1]", 0, 0, v9 }, /* flush rs1+0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "[i]", 0, 0, v9 }, /* flush %g0+i */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "[1+i]", 0, 0, v9 },
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "[i+1]", 0, 0, v9 },
+
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, 0, v8 },
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, 0, v8 }, /* flush rs1+%g0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", F_ALIAS, 0, v8 }, /* flush rs1+0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, 0, v8 }, /* flush %g0+i */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, 0, v8 },
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, 0, v8 },
 
 /* IFLUSH was renamed to FLUSH in v8.  */
 { "iflush",    F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, 0, v6 },
@@ -825,29 +860,34 @@ const struct sparc_opcode sparc_opcodes[] = {
 
 { "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", 0, 0, v8 }, /* wr r,r,%asrX */
 { "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", 0, 0, v8 }, /* wr r,i,%asrX */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),       "2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RS1_G0,               "i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI_RS2(~0),          "1,m", F_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),       "2,m", F_PREF_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RS1_G0,               "i,m", F_PREF_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|SIMM13(~0),           "1,m", F_PREF_ALIAS, 0, v8 }, /* wr rs1,%asrX */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI_RS2(~0),          "1,m", F_PREF_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */
 { "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", 0, 0, v6 }, /* wr r,r,%y */
 { "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", 0, 0, v6 }, /* wr r,i,%y */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,         "i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),    "1,y", F_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,         "i,y", F_PREF_ALIAS, 0, v6 }, /* wr %g0,i,%y */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),     "1,y", F_PREF_ALIAS, 0, v6 }, /* wr rs1,0,%y */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),    "1,y", F_PREF_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */
 { "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", 0, 0, v6notv9 }, /* wr r,r,%psr */
 { "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", 0, 0, v6notv9 }, /* wr r,i,%psr */
-{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
-{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,         "i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
-{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),    "1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */
+{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
+{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,         "i,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
+{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),     "1,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%psr */
+{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),    "1,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */
 { "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", 0, 0, v6notv9 }, /* wr r,r,%wim */
 { "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", 0, 0, v6notv9 }, /* wr r,i,%wim */
-{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
-{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,         "i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
-{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),    "1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */
+{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
+{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,         "i,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
+{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),     "1,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%wim */
+{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),    "1,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */
 { "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", 0, 0, v6notv9 }, /* wr r,r,%tbr */
 { "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", 0, 0, v6notv9 }, /* wr r,i,%tbr */
-{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
-{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,         "i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
-{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),    "1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
+{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
+{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,         "i,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
+{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),     "1,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%tbr */
+{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),    "1,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
 
 { "wr", F3(2, 0x30, 0)|RD(2),  F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),       "1,2,E", 0, 0, v9 }, /* wr r,r,%ccr */
 { "wr", F3(2, 0x30, 1)|RD(2),  F3(~2, ~0x30, ~1)|RD(~2),               "1,i,E", 0, 0, v9 }, /* wr r,i,%ccr */
@@ -903,9 +943,9 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "rd",        F3(2, 0x28, 0)|RS1(19),         F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %gsr,r */
 { "rd",        F3(2, 0x28, 0)|RS1(22),         F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %softint,r */
 { "rd",        F3(2, 0x28, 0)|RS1(23),         F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %tick_cmpr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(24),         F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),  "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(25),         F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),  "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick_cmpr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(26),         F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0),  "/,d", HWCAP_CBCOND, 0, v9b }, /* rd %cfr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(24),         F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),  "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(25),         F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),  "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick_cmpr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(26),         F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0),  "/,d", 0, HWCAP_CBCOND, v9b }, /* rd %cfr,r */
 { "rd",        F3(2, 0x28, 0)|RS1(28),         F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0),  "/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */
 
 { "rdpr",      F3(2, 0x2a, 0),         F3(~2, ~0x2a, ~0)|SIMM13(~0),   "?,d", 0, 0, v9 },   /* rdpr %priv,r */
@@ -922,18 +962,6 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "i,1,%", F_ALIAS, 0, v9 }, /* wrhpr i,r1,%hpriv */
 { "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RS1(~0),      "i,%", 0, 0, v9 },   /* wrhpr i,%hpriv */
 
-/* ??? This group seems wrong.  A three operand move?  */
-{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", F_ALIAS, 0, v8 }, /* wr r,r,%asrX */
-{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1),                      "1,i,m", F_ALIAS, 0, v8 }, /* wr r,i,%asrX */
-{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", F_ALIAS, 0, v6 }, /* wr r,r,%y */
-{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", F_ALIAS, 0, v6 }, /* wr r,i,%y */
-{ "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", F_ALIAS, 0, v6notv9 }, /* wr r,r,%psr */
-{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS, 0, v6notv9 }, /* wr r,i,%psr */
-{ "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", F_ALIAS, 0, v6notv9 }, /* wr r,r,%wim */
-{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS, 0, v6notv9 }, /* wr r,i,%wim */
-{ "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_ALIAS, 0, v6notv9 }, /* wr r,r,%tbr */
-{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS, 0, v6notv9 }, /* wr r,i,%tbr */
-
 { "mov",       F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", F_ALIAS, 0, v8 }, /* rd %asr1,r */
 { "mov",       F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", F_ALIAS, 0, v6 }, /* rd %y,r */
 { "mov",       F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", F_ALIAS, 0, v6notv9 }, /* rd %psr,r */
@@ -942,24 +970,14 @@ const struct sparc_opcode sparc_opcodes[] = {
 
 { "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),       "2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
 { "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0,               "i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
-{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),          "1,m", F_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */
-{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),           "1,m", F_ALIAS, 0, v8 }, /* wr rs1,0,%asrX */
 { "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
 { "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,         "i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */
-{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),    "1,y", F_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */
-{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),     "1,y", F_ALIAS, 0, v6 }, /* wr rs1,0,%y */
 { "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
 { "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,         "i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
-{ "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),    "1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */
-{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),     "1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%psr */
 { "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
 { "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,         "i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
-{ "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),    "1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */
-{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),     "1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%wim */
 { "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
 { "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,         "i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
-{ "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),    "1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
-{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),     "1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%tbr */
 
 { "mov",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),       "2,d", 0, 0, v6 }, /* or %g0,rs2,d */
 { "mov",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,               "i,d", 0, 0, v6 }, /* or %g0,i,d        */
@@ -1202,30 +1220,34 @@ cond ("bz",     "tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
 /* v9 */ condr("brlez", 0x2, F_CONDBR),
 /* v9 */ condr("brgz", 0x6, F_CONDBR),
 
-#define cbcond(cop, cmask) \
+#define cbcond(cop, cmask, flgs) \
   { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \
-    "1,2,=", F_CONDBR, HWCAP_CBCOND, v9}, \
+    "1,2,=", flgs, HWCAP_CBCOND, v9}, \
   { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \
-    "1,X,=", F_CONDBR, HWCAP_CBCOND, v9}, \
+    "1,X,=", flgs, HWCAP_CBCOND, v9}, \
   { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \
-    "1,2,=", F_CONDBR, HWCAP_CBCOND, v9}, \
+    "1,2,=", flgs, HWCAP_CBCOND, v9}, \
   { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \
-    "1,X,=", F_CONDBR, HWCAP_CBCOND, v9},
-
-cbcond("be",   0x09)
-cbcond("ble",  0x0a)
-cbcond("bl",   0x0b)
-cbcond("bleu", 0x0c)
-cbcond("bcs",  0x0d)
-cbcond("bneg", 0x0e)
-cbcond("bvs",  0x0f)
-cbcond("bne",  0x19)
-cbcond("bg",   0x1a)
-cbcond("bge",  0x1b)
-cbcond("bgu",  0x1c)
-cbcond("bcc",  0x1d)
-cbcond("bpos", 0x1e)
-cbcond("bvc",  0x1f)
+    "1,X,=", flgs, HWCAP_CBCOND, v9},
+
+cbcond("be",   0x09, F_CONDBR)
+cbcond("bz",   0x09, F_CONDBR|F_ALIAS)
+cbcond("ble",  0x0a, F_CONDBR)
+cbcond("bl",   0x0b, F_CONDBR)
+cbcond("bleu", 0x0c, F_CONDBR)
+cbcond("bcs",  0x0d, F_CONDBR)
+cbcond("blu",  0x0d, F_CONDBR|F_ALIAS)
+cbcond("bneg", 0x0e, F_CONDBR)
+cbcond("bvs",  0x0f, F_CONDBR)
+cbcond("bne",  0x19, F_CONDBR)
+cbcond("bnz",  0x19, F_CONDBR|F_ALIAS)
+cbcond("bg",   0x1a, F_CONDBR)
+cbcond("bge",  0x1b, F_CONDBR)
+cbcond("bgu",  0x1c, F_CONDBR)
+cbcond("bcc",  0x1d, F_CONDBR)
+cbcond("bgeu", 0x1d, F_CONDBR|F_ALIAS)
+cbcond("bpos", 0x1e, F_CONDBR)
+cbcond("bvc",  0x1f, F_CONDBR)
 
 #undef cbcond
 #undef condr /* v9 */
@@ -1806,54 +1828,89 @@ SLCBCC("cbnefr", 15),
 { "alignaddrl",        F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, v9a },
 { "faligndata",        F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, v9a },
 
-{ "fzero",     F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, v9a },
+{ "fzerod",    F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, v9a },
+{ "fzero",     F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, v9a },
 { "fzeros",    F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, v9a },
-{ "fone",      F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, v9a },
+{ "foned",     F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, v9a },
+{ "fone",      F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS, HWCAP_VIS, v9a },
 { "fones",     F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, v9a },
-{ "fsrc1",     F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, v9a },
+{ "fsrc1d",    F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, v9a },
+{ "fsrc1",     F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fsrc1s",    F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, v9a },
-{ "fsrc2",     F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, v9a },
+{ "fsrc2d",    F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, v9a },
+{ "fsrc2",     F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fsrc2s",    F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, v9a },
-{ "fnot1",     F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, v9a },
+{ "fnot1d",    F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, v9a },
+{ "fnot1",     F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fnot1s",    F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, v9a },
-{ "fnot2",     F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, v9a },
+{ "fnot2d",    F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, v9a },
+{ "fnot2",     F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fnot2s",    F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, v9a },
-{ "for",       F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "ford",      F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "for",       F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fors",      F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fnor",      F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fnord",     F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fnor",      F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fnors",     F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fand",      F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fandd",     F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fand",      F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fands",     F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fnand",     F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fnandd",    F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fnand",     F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fnands",    F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fxor",      F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fxord",     F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fxor",      F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fxors",     F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fxnor",     F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fxnord",    F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fxnor",     F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fxnors",    F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fornot1",   F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fornot1d",  F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fornot1",   F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fornot1s",  F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fornot2",   F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fornot2d",  F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fornot2",   F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fornot2s",  F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fandnot1",  F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fandnot1",  F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fandnot2",  F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, v9a },
+{ "fandnot2",  F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
 { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, v9a },
 
-{ "fcmpgt16",  F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmpgt32",  F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmple16",  F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmple32",  F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmpne16",  F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmpne32",  F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmpeq16",  F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmpeq32",  F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, v9a },
-
-{ "edge8",     F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge8l",    F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge16",    F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge16l",   F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge32",    F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge32l",   F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, v9a },
+{ "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fcmpgt16",  F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fcmpgt32",  F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fcmple16",  F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fcmple32",  F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fpcmpune16",        F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fcmpne16",  F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fpcmpune32",        F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fcmpne32",  F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fpcmpueq16",        F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fcmpeq16",  F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, v9a },
+{ "fpcmpueq32",        F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "fcmpeq32",  F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
+
+{ "edge8cc",   F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, v9a },
+{ "edge8lcc",  F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, v9a },
+{ "edge16cc",  F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, v9a },
+{ "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, v9a },
+{ "edge32cc",  F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, v9a },
+{ "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, v9a },
+
+{ "edge8",     F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "edge8l",    F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "edge16",    F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "edge16l",   F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "edge32",    F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
+{ "edge32l",   F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
 
 { "pdist",     F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, v9a },
 
@@ -1908,7 +1965,8 @@ SLCBCC("cbnefr", 15),
 { "addxccc",   F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, v9b },
 { "random",    F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT, HWCAP_RANDOM, v9b },
 { "umulxhi",   F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "lzd",       F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, v9b },
+{ "lzcnt",     F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, v9b },
+{ "lzd",       F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, v9b },
 { "cmask8",    F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, v9b },
 { "cmask16",   F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, v9b },
 { "cmask32",   F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, v9b },
@@ -1940,10 +1998,16 @@ SLCBCC("cbnefr", 15),
 { "movwtos",   F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, v9b },
 { "xmulx",     F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, v9b },
 { "xmulxhi",   F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "fucmple8",  F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fucmpne8",  F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fucmpgt8",  F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fucmpeq8",  F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
+{ "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, v9b },
+{ "fucmple8",  F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
+{ "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
+{ "fpcmpne8",  F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, v9b },
+{ "fucmpne8",  F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
+{ "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
+{ "fucmpgt8",  F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
+{ "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
+{ "fpcmpeq8",  F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, v9b },
+{ "fucmpeq8",  F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
 {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
 {"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
 { "des_ip",     F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, v9b },