arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs

Add the required 'mboxes' property to all the R5F processors for the
TI AM642 EVM and SK boards. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210615195718.15898-3-s-anna@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index dc69db2d10c347cfd78ac15d9af61c96a22f2b3d..2e75cd68f8b75e604e32fb0bd0c014945f5fd1ca 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -469,6 +469,22 @@
        status = "disabled";
 };
 
+&main_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+       mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+       mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+};
+
 &serdes_ln_ctrl {
        idle-states = <AM64_SERDES0_LANE0_PCIE0>;
 };

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 40124007259d2fe9a766b78db301ed0caae1f472..4abddea92cf5982ce7ba48d5189c05a0d4775a7c 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -368,6 +368,22 @@
        status = "disabled";
 };
 
+&main_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+       mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+       mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+};
+
 &pcie0_rc {
        status = "disabled";
 };