arm64: dts: Add the arasan mmc DTS entries for APm X-Gene v2 SoC
authorDuc Dang <dhdang@apm.com>
Wed, 16 Sep 2015 11:42:57 +0000 (17:12 +0530)
committerDuc Dang <dhdang@apm.com>
Tue, 17 Nov 2015 21:11:53 +0000 (13:11 -0800)
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene v2 SoC platforms.

Signed-off-by: Duc Dang <dhdang@apm.com>
arch/arm64/boot/dts/apm/apm-merlin.dts
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi

index 119a469..a0092f9 100644 (file)
@@ -70,3 +70,7 @@
 &xgenet1 {
        status = "ok";
 };
+
+&mmc0 {
+       status = "ok";
+};
index c804f8f..718ffc4 100644 (file)
                                clock-output-names = "socplldiv2";
                        };
 
+                       ahbclk: ahbclk@1f2ac000 {
+                               compatible = "apm,xgene-device-clock";
+                               #clock-cells = <1>;
+                               clocks = <&socplldiv2 0>;
+                               reg = <0x0 0x1f2ac000 0x0 0x1000
+                                       0x0 0x17000000 0x0 0x2000>;
+                               reg-names = "csr-reg", "div-reg";
+                               csr-offset = <0x0>;
+                               csr-mask = <0x1>;
+                               enable-offset = <0x8>;
+                               enable-mask = <0x1>;
+                               divider-offset = <0x164>;
+                               divider-width = <0x5>;
+                               divider-shift = <0x0>;
+                               clock-output-names = "ahbclk";
+                       };
+
+                       sdioclk: sdioclk@1f2ac000 {
+                               compatible = "apm,xgene-device-clock";
+                               #clock-cells = <1>;
+                               clocks = <&socplldiv2 0>;
+                               reg = <0x0 0x1f2ac000 0x0 0x1000
+                                       0x0 0x17000000 0x0 0x2000>;
+                               reg-names = "csr-reg", "div-reg";
+                               csr-offset = <0x0>;
+                               csr-mask = <0x2>;
+                               enable-offset = <0x8>;
+                               enable-mask = <0x2>;
+                               divider-offset = <0x178>;
+                               divider-width = <0x8>;
+                               divider-shift = <0x0>;
+                               clock-output-names = "sdioclk";
+                       };
+
                        pcie0clk: pcie0clk@1f2bc000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
                        dma-coherent;
                };
 
+               mmc0: mmc@1c000000 {
+                       compatible = "arasan,sdhci-4.9a";
+                       reg = <0x0 0x1c000000 0x0 0x100>;
+                       interrupts = <0x0 0x49 0x4>;
+                       dma-coherent;
+                       no-1-8-v;
+                       clock-names = "clk_xin", "clk_ahb";
+                       clocks = <&sdioclk 0>, <&ahbclk 0>;
+               };
+
                sbgpio: sbgpio@17001000{
                        compatible = "apm,xgene-gpio-sb";
                        reg = <0x0 0x17001000 0x0 0x400>;