(clrstrsi): New pattern and associate anonymous pattern.

From-SVN: r10843

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 4363315..9df676e 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5432,6 +5432,73 @@
   RET;
 }")
 
+(define_expand "clrstrsi"
+  [(set (match_dup 3) (const_int 0))
+   (parallel [(set (match_operand:BLK 0 "memory_operand" "")
+                  (const_int 0))
+             (use (match_operand:SI 1 "const_int_operand" ""))
+             (use (match_operand:SI 2 "const_int_operand" ""))
+             (use (match_dup 3))
+             (clobber (match_scratch:SI 4 ""))
+             (clobber (match_dup 5))])]
+  ""
+  "
+{
+  rtx addr0, addr1;
+
+  if (GET_CODE (operands[2]) != CONST_INT)
+    FAIL;
+
+  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
+
+  operands[3] = gen_reg_rtx (SImode);
+  operands[5] = addr0;
+
+  operands[0] = gen_rtx (MEM, BLKmode, addr0);
+}")
+
+;; It might seem that operand 0 could use predicate register_operand.
+;; But strength reduction might offset the MEM expression.  So we let
+;; reload put the address into %edi.
+
+(define_insn ""
+  [(set (mem:BLK (match_operand:SI 0 "address_operand" "D"))
+       (const_int 0))
+   (use (match_operand:SI 1 "const_int_operand" "n"))
+   (use (match_operand:SI 2 "immediate_operand" "i"))
+   (use (match_operand:SI 3 "register_operand" "a"))
+   (clobber (match_scratch:SI 4 "=&c"))
+   (clobber (match_dup 0))]
+  ""
+  "*
+{
+  rtx xops[2];
+
+  output_asm_insn (\"cld\", operands);
+  if (GET_CODE (operands[1]) == CONST_INT)
+    {
+      if (INTVAL (operands[1]) & ~0x03)
+       {
+         xops[0] = GEN_INT ((INTVAL (operands[1]) >> 2) & 0x3fffffff);
+         xops[1] = operands[4];
+
+         output_asm_insn (AS2 (mov%L1,%0,%1), xops);
+#ifdef INTEL_SYNTAX
+         output_asm_insn (\"rep stosd\", xops);
+#else
+         output_asm_insn (\"rep\;stosl\", xops);
+#endif
+       }
+      if (INTVAL (operands[1]) & 0x02)
+       output_asm_insn (\"stosw\", operands);
+      if (INTVAL (operands[1]) & 0x01)
+       output_asm_insn (\"stosb\", operands);
+    }
+  else
+    abort ();
+  RET;
+}")
+
 (define_expand "cmpstrsi"
   [(parallel [(set (match_operand:SI 0 "general_operand" "")
                   (compare:SI (match_operand:BLK 1 "general_operand" "")