vc4_hdmi: Adjust CEC ref clock based on its input clock

2711 uses a fixed 27MHz input, earlier models use the HSM clock

Signed-off-by: Dom Cobley <popcornmix@gmail.com>

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index bc6da63..baa8470 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -79,6 +79,7 @@
 # define VC4_HD_M_ENABLE                       BIT(0)
 
 #define CEC_CLOCK_FREQ 40000
+#define VC4_HSM_CLOCK 163682864
 
 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 {
@@ -755,8 +756,7 @@ static u32 vc4_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixe
         * needs to be a bit higher than the pixel clock rate
         * (generally 148.5Mhz).
         */
-
-       return 163682864;
+       return VC4_HSM_CLOCK;
 }
 
 static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
@@ -1399,6 +1399,7 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
        struct cec_connector_info conn_info;
        struct platform_device *pdev = vc4_hdmi->pdev;
        u32 value;
+       u32 clk_cnt;
        int ret;
 
        if (!vc4_hdmi->variant->cec_available)
@@ -1423,8 +1424,9 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
         * divider: the hsm_clock rate and this divider setting will
         * give a 40 kHz CEC clock.
         */
+       clk_cnt = vc4_hdmi->variant->cec_input_clock / CEC_CLOCK_FREQ;
        value |= VC4_HDMI_CEC_ADDR_MASK |
-                (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
+                ((clk_cnt-1) << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
        HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
        ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
                                        vc4_cec_irq_handler,
@@ -1769,6 +1771,7 @@ static int vc4_hdmi_dev_remove(struct platform_device *pdev)
 
 static const struct vc4_hdmi_variant bcm2835_variant = {
        .max_pixel_clock        = 162000000,
+       .cec_input_clock        = VC4_HSM_CLOCK,
        .audio_available        = true,
        .cec_available          = true,
        .registers              = vc4_hdmi_fields,
@@ -1793,6 +1796,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
        .id                     = 0,
        .audio_available        = true,
        .max_pixel_clock        = 297000000,
+       .cec_input_clock        = 27000000,
        .registers              = vc5_hdmi_hdmi0_fields,
        .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
        .phy_lane_mapping       = {
@@ -1820,6 +1824,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
        .id                     = 1,
        .audio_available        = true,
        .max_pixel_clock        = 297000000,
+       .cec_input_clock        = 27000000,
        .registers              = vc5_hdmi_hdmi1_fields,
        .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
        .phy_lane_mapping       = {

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 7765b9c..dbf96a3 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -48,6 +48,9 @@ struct vc4_hdmi_variant {
        /* Maximum pixel clock supported by the controller (in Hz) */
        unsigned long long max_pixel_clock;
 
+       /* Input clock frequency of CEC block (in Hz) */
+       unsigned long cec_input_clock;
+
        /* List of the registers available on that variant */
        const struct vc4_hdmi_register *registers;