.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
+ .multicast_ctrl_reg = 0x04,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
+ .multicast_ctrl_reg = 0x04,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
+ .multicast_ctrl_reg = 0x04,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x02,
.broadcast_ctrl_reg = 0x06,
+ .multicast_ctrl_reg = 0x04,
.supports_mii = {false, false, true},
.supports_rmii = {false, false, true},
.internal_phy = {true, true, false},
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false,
false, true, false},
.supports_rmii = {false, false, false, false,
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false,
false, true, true},
.supports_rmii = {false, false, false, false,
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, true},
.supports_rmii = {false, false, true},
.supports_rgmii = {false, false, true},
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false,
false, true, true},
.supports_rmii = {false, false, false, false,
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false, true, true},
.supports_rmii = {false, false, false, false, true, true},
.supports_rgmii = {false, false, false, false, true, true},
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
.reg_mib_cnt = MIB_COUNTER_NUM,
.stp_ctrl_reg = 0x0B04,
.broadcast_ctrl_reg = 0x0332,
+ .multicast_ctrl_reg = 0x0331,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
dev->dev_ops->enable_stp_addr(dev);
+ regmap_update_bits(dev->regmap[0], dev->info->multicast_ctrl_reg,
+ MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
+
ksz_init_mib_timer(dev);
ds->configure_vlan_while_not_filtering = false;