platform/x86: pmc_atom: Fix SLP_TYPx bitfield mask
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Mon, 1 Aug 2022 11:37:31 +0000 (14:37 +0300)
committerHans de Goede <hdegoede@redhat.com>
Mon, 15 Aug 2022 11:20:10 +0000 (13:20 +0200)
On Intel hardware the SLP_TYPx bitfield occupies bits 10-12 as per ACPI
specification (see Table 4.13 "PM1 Control Registers Fixed Hardware
Feature Control Bits" for the details).

Fix the mask and other related definitions accordingly.

Fixes: 93e5eadd1f6e ("x86/platform: New Intel Atom SOC power management controller driver")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220801113734.36131-1-andriy.shevchenko@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
drivers/platform/x86/pmc_atom.c
include/linux/platform_data/x86/pmc_atom.h

index 154317e..5c757c7 100644 (file)
@@ -232,7 +232,7 @@ static void pmc_power_off(void)
        pm1_cnt_port = acpi_base_addr + PM1_CNT;
 
        pm1_cnt_value = inl(pm1_cnt_port);
-       pm1_cnt_value &= SLEEP_TYPE_MASK;
+       pm1_cnt_value &= ~SLEEP_TYPE_MASK;
        pm1_cnt_value |= SLEEP_TYPE_S5;
        pm1_cnt_value |= SLEEP_ENABLE;
 
index 3edfb6d..dd81f51 100644 (file)
@@ -7,6 +7,8 @@
 #ifndef PMC_ATOM_H
 #define PMC_ATOM_H
 
+#include <linux/bits.h>
+
 /* ValleyView Power Control Unit PCI Device ID */
 #define        PCI_DEVICE_ID_VLV_PMC   0x0F1C
 /* CherryTrail Power Control Unit PCI Device ID */
 #define        ACPI_MMIO_REG_LEN       0x100
 
 #define        PM1_CNT                 0x4
-#define        SLEEP_TYPE_MASK         0xFFFFECFF
+#define        SLEEP_TYPE_MASK         GENMASK(12, 10)
 #define        SLEEP_TYPE_S5           0x1C00
-#define        SLEEP_ENABLE            0x2000
+#define        SLEEP_ENABLE            BIT(13)
 
 extern int pmc_atom_read(int offset, u32 *value);