arm64: dts: keembay: Add device tree for Keem Bay SoC

Add initial device tree for Intel Movidius SoC code-named Keem Bay.

This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI,
and PMU.

Link: https://lore.kernel.org/r/20200717090414.313530-5-daniele.alessandrelli@linux.intel.com
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/MAINTAINERS b/MAINTAINERS
index fd46dfc..5bcd1c4 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1959,6 +1959,7 @@ M:        Paul J. Murphy <paul.j.murphy@intel.com>
 M:     Daniele Alessandrelli <daniele.alessandrelli@intel.com>
 S:     Maintained
 F:     Documentation/devicetree/bindings/arm/intel,keembay.yaml
+F:     arch/arm64/boot/dts/intel/keembay-soc.dtsi
 
 ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
 M:     Jonathan Cameron <jic23@cam.ac.uk>

diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
new file mode 100644 (file)
index 0000000..781761d
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020, Intel Corporation.
+ *
+ * Device tree describing Keem Bay SoC.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       enable-method = "psci";
+               };
+
+               cpu@1 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x1>;
+                       enable-method = "psci";
+               };
+
+               cpu@2 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x2>;
+                       enable-method = "psci";
+               };
+
+               cpu@3 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x3>;
+                       enable-method = "psci";
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       gic: interrupt-controller@20500000 {
+               compatible = "arm,gic-v3";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               reg = <0x0 0x20500000 0x0 0x20000>,     /* GICD */
+                     <0x0 0x20580000 0x0 0x80000>;     /* GICR */
+               /* VGIC maintenance interrupt */
+               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               /* Secure, non-secure, virtual, and hypervisor */
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       pmu {
+               compatible = "arm,armv8-pmuv3";
+               interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               uart0: serial@20150000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x20150000 0x0 0x100>;
+                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <24000000>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               uart1: serial@20160000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x20160000 0x0 0x100>;
+                       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <24000000>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               uart2: serial@20170000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x20170000 0x0 0x100>;
+                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <24000000>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               uart3: serial@20180000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x20180000 0x0 0x100>;
+                       interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <24000000>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+       };
+};