BZ: 26839
Add DRM_CTP_PR1 into Kconfig, and SGX544MP2's register bar length is
0x10000
Change-Id: I355ca4c08b0cc79877fb1e538c9725f44bbf20ba
Signed-off-by: Yun(Mark) Tu <yun.tu@intel.com>
Reviewed-on: http://android.intel.com:8080/41511
Reviewed-by: Ponnusamy, Siva Prasath <siva.prasath.ponnusamy@intel.com>
Reviewed-by: Dai, Yu <yu.dai@intel.com>
Reviewed-by: Xu, Randy <randy.xu@intel.com>
Tested-by: Xu, Randy <randy.xu@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
platform. If M is selected the module will be called
mid_gfx.
+config DRM_CTP_PR1
+ tristate "Intel Clover Trail Phone for SGX544MP2(CTP)"
+ depends on DRM_CTP
+ help
+ Choose this option if you have a Clover Trail Phone
+ platform. If M is selected the module will be called
+ mid_gfx.
+
config MDFLD_DSI_DSR
bool "Support DSI Fullscreen Display Self Refreshment "
depends on (DRM_MDFLD || DRM_CTP) && !MDFLD_DSI_DPU
#define POULSBO_REG_SIZE 0x2100
#define SGX_REGS_OFFSET 0x80000
-#define SGX_REG_SIZE 0x4000
+#if defined(SGX544)
+#define SGX_REG_SIZE 0x10000
+#else
+#define SGX_REG_SIZE 0x4000
+#endif
#define MRST_SGX_REGS_OFFSET SGX_REGS_OFFSET
#define POULSBO_SGX_REGS_OFFSET 0x40000