{
VkShaderModule mod = VK_NULL_HANDLE;
void *streamout = NULL;
+ nir_shader *nir = zs->nir;
+ /* TODO: use a separate mem ctx here for ralloc */
if (zs->streamout.so_info_slots && (zs->nir->info.stage != MESA_SHADER_VERTEX || !zs->has_geometry_shader))
streamout = &zs->streamout;
- struct spirv_shader *spirv = nir_to_spirv(zs->nir, streamout, shader_slot_map, shader_slots_reserved);
+ if (zs->nir->info.stage == MESA_SHADER_FRAGMENT) {
+ nir = nir_shader_clone(NULL, nir);
+ if (!zink_fs_key(key)->samples &&
+ nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)) {
+ /* VK will always use gl_SampleMask[] values even if sample count is 0,
+ * so we need to skip this write here to mimic GL's behavior of ignoring it
+ */
+ nir_foreach_shader_out_variable(var, nir) {
+ if (var->data.location == FRAG_RESULT_SAMPLE_MASK)
+ var->data.mode = nir_var_shader_temp;
+ }
+ nir_fixup_deref_modes(nir);
+ NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_shader_temp, NULL);
+ optimize_nir(nir);
+ }
+ }
+ struct spirv_shader *spirv = nir_to_spirv(nir, streamout, shader_slot_map, shader_slots_reserved);
assert(spirv);
if (zink_debug & ZINK_DEBUG_SPIRV) {
if (vkCreateShaderModule(screen->dev, &smci, NULL, &mod) != VK_SUCCESS)
mod = VK_NULL_HANDLE;
+ if (zs->nir->info.stage == MESA_SHADER_FRAGMENT)
+ ralloc_free(nir);
+
/* TODO: determine if there's any reason to cache spirv output? */
free(spirv->words);
free(spirv);
zink_framebuffer_reference(screen, &ctx->framebuffer, fb);
zink_render_pass_reference(screen, &ctx->gfx_pipeline_state.render_pass, fb->rp);
- ctx->gfx_pipeline_state.rast_samples = util_framebuffer_get_num_samples(state);
+ uint8_t rast_samples = util_framebuffer_get_num_samples(state);
+ /* in vulkan, gl_SampleMask needs to be explicitly ignored for sampleCount == 1 */
+ if ((ctx->gfx_pipeline_state.rast_samples > 1) != (rast_samples > 1))
+ ctx->dirty_shader_stages |= 1 << PIPE_SHADER_FRAGMENT;
+ ctx->gfx_pipeline_state.rast_samples = rast_samples;
ctx->gfx_pipeline_state.num_attachments = state->nr_cbufs;
ctx->gfx_pipeline_state.hash = 0;