warp7: Fix watchdog reset

The latest version of warp7 board provides the connection of the
WDOG1_B pin to the PMIC.

Program the watchdog to enable the WDOG1_B output which causes
a POR reset.

Based on the imx7dsabresd code.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index 8c5bf9a..27e31f3 100644 (file)
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -32,6 +32,10 @@ int dram_init(void)
        return 0;
 }
 
+static iomux_v3_cfg_t const wdog_pads[] = {
+       MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const uart1_pads[] = {
        MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -100,3 +104,20 @@ int board_usb_phy_mode(int port)
 {
        return USB_INIT_DEVICE;
 }
+
+int board_late_init(void)
+{
+       struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+       imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+       set_wdog_reset(wdog);
+
+       /*
+        * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+        * since we use PMIC_PWRON to reset the board.
+        */
+       clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+       return 0;
+}

diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index f112fa5..8b9ed2b 100644 (file)
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_MALLOC_LEN          (32 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 
 /* MMC Config*/
 #define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR