radv: enable sisched toggle in perftest flags.
authorDave Airlie <airlied@redhat.com>
Thu, 6 Jul 2017 02:06:01 +0000 (03:06 +0100)
committerDave Airlie <airlied@redhat.com>
Thu, 6 Jul 2017 22:07:49 +0000 (23:07 +0100)
RADV_PERFTEST=sisched

to enable it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
src/amd/common/ac_llvm_util.c
src/amd/common/ac_llvm_util.h
src/amd/vulkan/radv_debug.h
src/amd/vulkan/radv_device.c
src/amd/vulkan/radv_pipeline.c

index 84ed73f..d14057f 100644 (file)
@@ -126,8 +126,9 @@ LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum ac
        LLVMTargetRef target = ac_get_llvm_target(triple);
 
        snprintf(features, sizeof(features),
-                "+DumpCode,+vgpr-spilling,-fp32-denormals%s",
-                family >= CHIP_VEGA10 ? ",+xnack" : ",-xnack");
+                "+DumpCode,+vgpr-spilling,-fp32-denormals%s%s",
+                family >= CHIP_VEGA10 ? ",+xnack" : ",-xnack",
+                tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "");
        
        LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
                                     target,
index 06208a4..21f3e83 100644 (file)
@@ -56,6 +56,7 @@ enum ac_func_attr {
 
 enum ac_target_machine_options {
        AC_TM_SUPPORTS_SPILL = (1 << 0),
+       AC_TM_SISCHED = (1 << 1),
 };
 LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum ac_target_machine_options tm_options);
 
index c986c7b..c345d04 100644 (file)
@@ -39,5 +39,6 @@ enum {
 
 enum {
        RADV_PERFTEST_BATCHCHAIN     =   0x1,
+       RADV_PERFTEST_SISCHED        =   0x2,
 };
 #endif
index 8cf5442..d1c519a 100644 (file)
@@ -370,6 +370,7 @@ static const struct debug_control radv_debug_options[] = {
 
 static const struct debug_control radv_perftest_options[] = {
        {"batchchain", RADV_PERFTEST_BATCHCHAIN},
+       {"sisched", RADV_PERFTEST_SISCHED},
        {NULL, 0}
 };
 
index 71a5cce..90cd716 100644 (file)
@@ -467,6 +467,8 @@ static struct radv_shader_variant *radv_shader_variant_create(struct radv_device
        options.supports_spill = device->llvm_supports_spill;
        if (options.supports_spill)
                tm_options |= AC_TM_SUPPORTS_SPILL;
+       if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
+               tm_options |= AC_TM_SISCHED;
        tm = ac_create_target_machine(chip_family, tm_options);
        ac_compile_nir_shader(tm, &binary, &variant->config,
                              &variant->info, shader, &options, dump);
@@ -508,6 +510,8 @@ radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
        options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
        if (options.supports_spill)
                tm_options |= AC_TM_SUPPORTS_SPILL;
+       if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
+               tm_options |= AC_TM_SISCHED;
        tm = ac_create_target_machine(chip_family, tm_options);
        ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
        LLVMDisposeTargetMachine(tm);