dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
authorNeil Armstrong <neil.armstrong@linaro.org>
Mon, 12 Jun 2023 09:57:30 +0000 (11:57 +0200)
committerJerome Brunet <jbrunet@baylibre.com>
Tue, 8 Aug 2023 14:06:17 +0000 (16:06 +0200)
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every A1 pll ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/a1-pll.h
include/dt-bindings/clock/amlogic,a1-pll-clkc.h

index 8257075..0add1c7 100644 (file)
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
 
-/*
- * CLKID index values for internal clocks
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_FIXED_PLL_DCO    0
-#define CLKID_FCLK_DIV2_DIV    2
-#define CLKID_FCLK_DIV3_DIV    3
-#define CLKID_FCLK_DIV5_DIV    4
-#define CLKID_FCLK_DIV7_DIV    5
-
 #endif /* __A1_PLL_H */
index 01fb816..2b660c0 100644 (file)
 #ifndef __A1_PLL_CLKC_H
 #define __A1_PLL_CLKC_H
 
+#define CLKID_FIXED_PLL_DCO    0
 #define CLKID_FIXED_PLL                1
+#define CLKID_FCLK_DIV2_DIV    2
+#define CLKID_FCLK_DIV3_DIV    3
+#define CLKID_FCLK_DIV5_DIV    4
+#define CLKID_FCLK_DIV7_DIV    5
 #define CLKID_FCLK_DIV2                6
 #define CLKID_FCLK_DIV3                7
 #define CLKID_FCLK_DIV5                8