clk: socfpga: Don't reference clk_init_data after registration

A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-7-sboyd@kernel.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 3966cd4..2a5876d 100644 (file)
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -30,21 +30,22 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
        u32 l4_src;
        u32 perpll_src;
+       const char *name = clk_hw_get_name(hwclk);
 
-       if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+       if (streq(name, SOCFPGA_L4_MP_CLK)) {
                l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
                return l4_src &= 0x1;
        }
-       if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+       if (streq(name, SOCFPGA_L4_SP_CLK)) {
                l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
                return !!(l4_src & 2);
        }
 
        perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-       if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+       if (streq(name, SOCFPGA_MMC_CLK))
                return perpll_src &= 0x3;
-       if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
-                       streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+       if (streq(name, SOCFPGA_NAND_CLK) ||
+                       streq(name, SOCFPGA_NAND_X_CLK))
                        return (perpll_src >> 2) & 3;
 
        /* QSPI clock */
@@ -55,24 +56,25 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
 {
        u32 src_reg;
+       const char *name = clk_hw_get_name(hwclk);
 
-       if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+       if (streq(name, SOCFPGA_L4_MP_CLK)) {
                src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
                src_reg &= ~0x1;
                src_reg |= parent;
                writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
-       } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+       } else if (streq(name, SOCFPGA_L4_SP_CLK)) {
                src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
                src_reg &= ~0x2;
                src_reg |= (parent << 1);
                writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
        } else {
                src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-               if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+               if (streq(name, SOCFPGA_MMC_CLK)) {
                        src_reg &= ~0x3;
                        src_reg |= parent;
-               } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
-                       streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+               } else if (streq(name, SOCFPGA_NAND_CLK) ||
+                       streq(name, SOCFPGA_NAND_X_CLK)) {
                        src_reg &= ~0xC;
                        src_reg |= (parent << 2);
                } else {/* QSPI clock */

diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index a8ff722..3e0c557 100644 (file)
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -40,11 +40,12 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
 {
        struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
        u32 clk_src;
+       const char *name = clk_hw_get_name(hwclk);
 
        clk_src = readl(socfpgaclk->hw.reg);
-       if (streq(hwclk->init->name, SOCFPGA_MPU_FREE_CLK) ||
-           streq(hwclk->init->name, SOCFPGA_NOC_FREE_CLK) ||
-           streq(hwclk->init->name, SOCFPGA_SDMMC_FREE_CLK))
+       if (streq(name, SOCFPGA_MPU_FREE_CLK) ||
+           streq(name, SOCFPGA_NOC_FREE_CLK) ||
+           streq(name, SOCFPGA_SDMMC_FREE_CLK))
                return (clk_src >> CLK_MGR_FREE_SHIFT) &
                        CLK_MGR_FREE_MASK;
        else