uint32_t cycles;
uint32_t spills;
uint32_t fills;
+ uint32_t max_live_registers;
};
/** @} */
return progress;
}
+uint32_t
+fs_visitor::compute_max_register_pressure()
+{
+ const register_pressure &rp = regpressure_analysis.require();
+ uint32_t ip = 0, max_pressure = 0;
+ foreach_block_and_inst(block, backend_instruction, inst, cfg) {
+ max_pressure = MAX2(max_pressure, rp.regs_live_at_ip[ip]);
+ ip++;
+ }
+ return max_pressure;
+}
+
void
fs_visitor::allocate_registers(bool allow_spilling)
{
"lifo"
};
+ if (needs_register_pressure)
+ shader_stats.max_register_pressure = compute_max_register_pressure();
+
bool spill_all = allow_spilling && INTEL_DEBUG(DEBUG_SPILL_FS);
/* Before we schedule anything, stash off the instruction order as an array
v8 = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base, nir, 8,
+ params->stats != NULL,
debug_enabled);
if (!v8->run_fs(allow_spilling, false /* do_rep_send */)) {
params->error_str = ralloc_strdup(mem_ctx, v8->fail_msg);
/* Try a SIMD16 compile */
v16 = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base, nir, 16,
+ params->stats != NULL,
debug_enabled);
v16->import_uniforms(v8.get());
if (!v16->run_fs(allow_spilling, params->use_rep_send)) {
/* Try a SIMD32 compile */
v32 = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base, nir, 32,
+ params->stats != NULL,
debug_enabled);
v32->import_uniforms(v8.get());
if (!v32->run_fs(allow_spilling, false)) {
key->base.robust_buffer_access);
v[simd] = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
- &prog_data->base, shader, dispatch_width,
+ &prog_data->base, shader, dispatch_width,
+ params->stats != NULL,
debug_enabled);
const int first = brw_simd_first_compiled(simd_state);
v[simd] = std::make_unique<fs_visitor>(compiler, log_data, mem_ctx, &key->base,
&prog_data->base, shader,
- dispatch_width, debug_enabled);
+ dispatch_width,
+ stats != NULL,
+ debug_enabled);
const bool allow_spilling = !brw_simd_any_compiled(simd_state);
if (v[simd]->run_bs(allow_spilling)) {
unsigned promoted_constants;
unsigned spill_count;
unsigned fill_count;
+ unsigned max_register_pressure;
};
/** Register numbers for thread payload fields. */
struct brw_stage_prog_data *prog_data,
const nir_shader *shader,
unsigned dispatch_width,
+ bool needs_register_pressure,
bool debug_enabled);
fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
struct brw_gs_compile *gs_compile,
struct brw_gs_prog_data *prog_data,
const nir_shader *shader,
+ bool needs_register_pressure,
bool debug_enabled);
void init();
~fs_visitor();
bool run_mesh(bool allow_spilling);
void optimize();
void allocate_registers(bool allow_spilling);
+ uint32_t compute_max_register_pressure();
bool fixup_sends_duplicate_payload();
void fixup_3src_null_dest();
void emit_dummy_memory_fence_before_eot();
unsigned grf_used;
bool spilled_any_registers;
+ bool needs_register_pressure;
const unsigned dispatch_width; /**< 8, 16 or 32 */
unsigned max_dispatch_width;
stats->cycles = perf.latency;
stats->spills = shader_stats.spill_count;
stats->fills = shader_stats.fill_count;
+ stats->max_live_registers = shader_stats.max_register_pressure;
}
return start_offset;
struct brw_stage_prog_data *prog_data,
const nir_shader *shader,
unsigned dispatch_width,
+ bool needs_register_pressure,
bool debug_enabled)
: backend_shader(compiler, log_data, mem_ctx, shader, prog_data,
debug_enabled),
key(key), gs_compile(NULL), prog_data(prog_data),
live_analysis(this), regpressure_analysis(this),
performance_analysis(this),
+ needs_register_pressure(needs_register_pressure),
dispatch_width(dispatch_width),
bld(fs_builder(this, dispatch_width).at_end())
{
struct brw_gs_compile *c,
struct brw_gs_prog_data *prog_data,
const nir_shader *shader,
+ bool needs_register_pressure,
bool debug_enabled)
: backend_shader(compiler, log_data, mem_ctx, shader,
&prog_data->base.base, debug_enabled),
prog_data(&prog_data->base.base),
live_analysis(this), regpressure_analysis(this),
performance_analysis(this),
+ needs_register_pressure(needs_register_pressure),
dispatch_width(8),
bld(fs_builder(this, dispatch_width).at_end())
{
this->last_scratch = 0;
this->push_constant_loc = NULL;
- this->shader_stats.scheduler_mode = NULL;
- this->shader_stats.promoted_constants = 0,
- this->shader_stats.spill_count = 0,
- this->shader_stats.fill_count = 0,
+ memset(&this->shader_stats, 0, sizeof(this->shader_stats));
this->grf_used = 0;
this->spilled_any_registers = false;
v[simd] = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base.base, shader, dispatch_width,
+ params->stats != NULL,
debug_enabled);
if (prog_data->base.prog_mask) {
v[simd] = std::make_unique<fs_visitor>(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base.base, shader, dispatch_width,
+ params->stats != NULL,
debug_enabled);
if (prog_data->base.prog_mask) {
if (is_scalar) {
fs_visitor v(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base.base, nir, 8,
- debug_enabled);
+ params->stats != NULL, debug_enabled);
if (!v.run_tes()) {
params->error_str = ralloc_strdup(mem_ctx, v.fail_msg);
return NULL;
fs_visitor v(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base.base, nir, 8,
- debug_enabled);
+ params->stats != NULL, debug_enabled);
if (!v.run_vs()) {
params->error_str = ralloc_strdup(mem_ctx, v.fail_msg);
return NULL;
if (is_scalar) {
fs_visitor v(compiler, params->log_data, mem_ctx, &c, prog_data, nir,
- debug_enabled);
+ params->stats != NULL, debug_enabled);
if (v.run_gs()) {
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs;
if (is_scalar) {
fs_visitor v(compiler, params->log_data, mem_ctx, &key->base,
- &prog_data->base.base, nir, 8, debug_enabled);
+ &prog_data->base.base, nir, 8, params->stats != NULL,
+ debug_enabled);
if (!v.run_tcs()) {
params->error_str = ralloc_strdup(mem_ctx, v.fail_msg);
return NULL;
struct brw_wm_prog_data *prog_data,
nir_shader *shader)
: fs_visitor(compiler, NULL, mem_ctx, NULL,
- &prog_data->base, shader, 8, false) {}
+ &prog_data->base, shader, 8, false, false) {}
};
struct brw_wm_prog_data *prog_data,
nir_shader *shader)
: fs_visitor(compiler, NULL, mem_ctx, NULL,
- &prog_data->base, shader, 8, false) {}
+ &prog_data->base, shader, 8, false, false) {}
};
struct brw_wm_prog_data *prog_data,
nir_shader *shader)
: fs_visitor(compiler, NULL, mem_ctx, NULL,
- &prog_data->base, shader, 16, false) {}
+ &prog_data->base, shader, 16, false, false) {}
};
nir_shader *shader =
nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL);
- v = new fs_visitor(compiler, NULL, ctx, NULL, &prog_data->base, shader, 8, false);
+ v = new fs_visitor(compiler, NULL, ctx, NULL, &prog_data->base, shader, 8,
+ false, false);
devinfo->ver = 12;
devinfo->verx10 = devinfo->ver * 10;