clk: ux500: Define smp_twd clock for u8500

The smp_twd clock is based upon a prcmu_rate clock type
for the PRCMU_ARMSS clock.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 5c1fca1..ca4a25e 100644 (file)
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -205,12 +205,16 @@ void u8500_clk_init(void)
        clk_register_clkdev(clk, "dsilp2", "dsilink.2");
        clk_register_clkdev(clk, "dsilp2", "mcde");
 
+       clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
+                               CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
+                               CLK_IGNORE_UNUSED);
+       clk_register_clkdev(clk, NULL, "smp_twd");
+
        /*
         * FIXME: Add special handled PRCMU clocks here:
-        * 1. smp_twd, use PRCMU_ARMSS.
-        * 2. clk_arm, use PRCMU_ARMCLK.
-        * 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
-        * 4. ab9540_clkout1yuv, see clkout0yuv
+        * 1. clk_arm, use PRCMU_ARMCLK.
+        * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
+        * 3. ab9540_clkout1yuv, see clkout0yuv
         */
 
        /* PRCC P-clocks */