radeonsi/gfx10: set cache control registers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 9f3e086..27e42d8 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5567,6 +5567,25 @@ static void si_init_config(struct si_context *sctx)
                               S_028C50_MAX_DEALLOCS_IN_WAVE(512));
                si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
                               sscreen->info.pa_sc_tile_steering_override);
+
+               si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
+                              S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                              S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                              S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                              S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                              S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
+                              S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
+                              S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
+
+               si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
+                              S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                              S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                              S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                              S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                              S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
+                              S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
+                              S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
+                              S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
        }
 
        if (sctx->chip_class >= GFX8) {