hdmirx: increase waiting time of tmds valid [1/1]

PD#SWPL-8032

Problem:
Switching to HDMI source is slower than T962

Solution:
ensure pll lock is table before do DWC reset

Verify:
T962X2

Change-Id: I1133d6b1fb532ab8460c1906a021fe133ea9fb83
Signed-off-by: Lei Yang <lei.yang@amlogic.com>

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
index d924077..7c22071 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
@@ -34,7 +34,7 @@
 #include "hdmi_rx_edid.h"
 
 
-#define RX_VER0 "ver.2019-04-29"
+#define RX_VER0 "ver.2019-05-01"
 /*
  *
  *

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
index 082b31d..6cafe4b 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -4055,8 +4055,10 @@ void rx_emp_to_ddr_init(void)
                /* emp int enable TOP_INTR_MASKN*/
                /* emp field end done at DE rist bit[25]*/
                /* emp last EMP pkt recv done bit[26]*/
-               top_intr_maskn_value |= _BIT(25);
-               hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);
+               /* disable emp irq */
+               /* top_intr_maskn_value |= _BIT(25);
+                * hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);
+                */
        }
 
        rx.empbuff.ready = NULL;

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
index 207ee8e..19e2d35 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
@@ -49,7 +49,7 @@ static int pll_unlock_cnt;
 static int pll_unlock_max = 30;
 
 static int pll_lock_cnt;
-static int pll_lock_max = 2;
+static int pll_lock_max;
 
 static int dwc_rst_wait_cnt;
 static int dwc_rst_wait_cnt_max = 1;
@@ -215,7 +215,7 @@ void hdmirx_init_params(void)
                clk_unstable_max = 10;
                esd_phy_rst_max = 20;
                stable_check_lvl = 0x7df;
-               pll_lock_max = 1;
+               pll_lock_max = 5;
        } else {
                clk_unstable_max = 200;
                esd_phy_rst_max = 2;
@@ -1726,6 +1726,8 @@ int rx_set_global_variable(const char *buf, int size)
                return pr_var(cdr_lock_level, index);
        if (set_pr_var(tmpbuf, top_intr_maskn_value, value, &index, ret))
                return pr_var(top_intr_maskn_value, index);
+       if (set_pr_var(tmpbuf, pll_lock_max, value, &index, ret))
+               return pr_var(pll_lock_max, index);
        return 0;
 }
 
@@ -1835,6 +1837,7 @@ void rx_get_global_variable(const char *buf)
        pr_var(hbr_force_8ch, i++);
        pr_var(cdr_lock_level, i++);
        pr_var(top_intr_maskn_value, i++);
+       pr_var(pll_lock_max, i++);
 }
 
 void skip_frame(unsigned int cnt)