ARM64: dts: meson: add MMC resets
authorJerome Brunet <jbrunet@baylibre.com>
Thu, 26 Apr 2018 10:41:19 +0000 (12:41 +0200)
committerKevin Hilman <khilman@baylibre.com>
Wed, 9 May 2018 22:14:50 +0000 (15:14 -0700)
Add reset lines to the mmc controllers of the meson gx and axg SoCs

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

index a3a0fd5..381bd2c 100644 (file)
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/axg-clkc.h>
 #include <dt-bindings/gpio/meson-axg-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
 
 / {
        compatible = "amlogic,meson-axg";
                                        <&clkc CLKID_SD_EMMC_B_CLK0>,
                                        <&clkc CLKID_FCLK_DIV2>;
                                clock-names = "core", "clkin0", "clkin1";
+                               resets = <&reset RESET_SD_EMMC_B>;
                        };
 
                        sd_emmc_c: mmc@7000 {
                                        <&clkc CLKID_SD_EMMC_C_CLK0>,
                                        <&clkc CLKID_FCLK_DIV2>;
                                clock-names = "core", "clkin0", "clkin1";
+                               resets = <&reset RESET_SD_EMMC_C>;
                        };
                };
 
index c3b8e0d..1cbb082 100644 (file)
                 <&clkc CLKID_SD_EMMC_A_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_A>;
 };
 
 &sd_emmc_b {
                 <&clkc CLKID_SD_EMMC_B_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_B>;
 };
 
 &sd_emmc_c {
                 <&clkc CLKID_SD_EMMC_C_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_C>;
 };
 
 &spicc {
index 00b5bbd..6e4a071 100644 (file)
                 <&clkc CLKID_SD_EMMC_A_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_A>;
 };
 
 &sd_emmc_b {
        clocks = <&clkc CLKID_SD_EMMC_B>,
                 <&clkc CLKID_SD_EMMC_B_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
-       clock-names = "core", "clkin0", "clkin1";
+       clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_B>;
 };
 
 &sd_emmc_c {
                 <&clkc CLKID_SD_EMMC_C_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_C>;
 };
 
 &spicc {