[RISCV] Correct alignment settings for vector registers.

According to "9. Vector Memory Alignment Constraints" in V
specification, the alignment of vector memory access is aligned to the
size of the element. In our current implementation, we support ELEN up
to 64. We could assume the alignment of vector registers is 64 under the
assumption.

Differential Revision: https://reviews.llvm.org/D94751

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 99f74bf..75615fd 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -386,11 +386,10 @@ let RegAltNameIndices = [ABIRegAltName] in {
 class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
   : RegisterClass<"RISCV",
                   regTypes,
-                  // FIXME: Spill alignment set to 16 bytes.
-                  128,
+                  64, // The maximum supported ELEN is 64.
                   regList> {
   int VLMul = Vlmul;
-  int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64
+  int Size = !mul(Vlmul, 64);
 }
 
 def VR : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t,