phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration

Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change
to Gen1 during initialization. This helps in the below surprise link down
cases,
  - Surprise link down happens at Gen3/Gen4 link speed.
  - Surprise link down happens and external REFCLK is cut off, which causes
UPHY PLL rate to deviate to an invalid rate.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://lore.kernel.org/r/20221013183854.21087-9-vidyas@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index 1415ca7..633e6b7 100644 (file)
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -15,6 +15,7 @@
 #include <linux/phy/phy.h>
 
 #define P2U_CONTROL_CMN                        0x74
+#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE             BIT(13)
 #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN                 BIT(20)
 
 #define P2U_PERIODIC_EQ_CTRL_GEN3      0xc0
@@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x)
        return 0;
 }
 
+static int tegra_p2u_calibrate(struct phy *x)
+{
+       struct tegra_p2u *phy = phy_get_drvdata(x);
+       u32 val;
+
+       val = p2u_readl(phy, P2U_CONTROL_CMN);
+       val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE;
+       p2u_writel(phy, val, P2U_CONTROL_CMN);
+
+       return 0;
+}
+
 static const struct phy_ops ops = {
        .power_on = tegra_p2u_power_on,
+       .calibrate = tegra_p2u_calibrate,
        .owner = THIS_MODULE,
 };