dma: dma-controller@16050000 {
compatible = "starfive,axi-dma";
reg = <0x0 0x16050000 0x0 0x10000>;
- clocks = <&stg_axiahb_clk>, <&stg_apbclk>;
+ clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
+ <&clkgen JH7110_DMA1P_CLK_AHB>;
clock-names = "core-clk", "cfgr-clk";
+ resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
+ <&rstgen RSTN_U0_DW_DMA1P_AHB>;
+ reset-names = "rst_axi",
+ "rst_ahb";
interrupts = <73>;
#dma-cells = <2>;
dma-channels = <4>;
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/types.h>
+#include <linux/reset.h>
#include "dw-axi-dmac.h"
#include "../dmaengine.h"
if (IS_ERR(chip->cfgr_clk))
return PTR_ERR(chip->cfgr_clk);
+ chip->rst_core = devm_reset_control_get_exclusive(&pdev->dev, "rst_axi");
+ if (IS_ERR(chip->rst_core)) {
+ dev_err(&pdev->dev, "%s: failed to get rst_core reset control\n", __func__);
+ return PTR_ERR(chip->rst_core);
+ }
+ chip->rst_cfgr = devm_reset_control_get_exclusive(&pdev->dev, "rst_ahb");
+ if (IS_ERR(chip->rst_cfgr)) {
+ dev_err(&pdev->dev, "%s: failed to get rst_cfgr reset control\n", __func__);
+ return PTR_ERR(chip->rst_cfgr);
+ }
+
+ reset_control_deassert(chip->rst_core);
+ reset_control_deassert(chip->rst_cfgr);
+
ret = parse_device_properties(chip);
if (ret)
return ret;