net/mlx5: DR, Support matching on tunnel headers 0 and 1
authorMuhammad Sammar <muhammads@nvidia.com>
Sun, 5 Sep 2021 14:07:49 +0000 (17:07 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Fri, 31 Dec 2021 08:17:30 +0000 (00:17 -0800)
Tunnel headers are generic encapsulation headers, applies for all
tunneling protocols identified by the device native parser or by the
programmable parser, this support will enable raw matching headers 0 and 1.

Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h

index 856541a60d8c69e57f5845004bfea921e975a3cf..b3e7a611f99ecea6ea382438f77f8ec569f93364 100644 (file)
@@ -368,6 +368,12 @@ static bool dr_mask_is_tnl_mpls_over_udp(struct mlx5dr_match_param *mask,
        return DR_MASK_IS_OUTER_MPLS_OVER_UDP_SET(&mask->misc2) &&
               dr_matcher_supp_tnl_mpls_over_udp(&dmn->info.caps);
 }
+
+static bool dr_mask_is_tnl_header_0_1_set(struct mlx5dr_match_misc5 *misc5)
+{
+       return misc5->tunnel_header_0 || misc5->tunnel_header_1;
+}
+
 int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher,
                                   struct mlx5dr_matcher_rx_tx *nic_matcher,
                                   enum mlx5dr_ipv outer_ipv,
@@ -446,7 +452,8 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher,
        if (matcher->match_criteria & (DR_MATCHER_CRITERIA_OUTER |
                                       DR_MATCHER_CRITERIA_MISC |
                                       DR_MATCHER_CRITERIA_MISC2 |
-                                      DR_MATCHER_CRITERIA_MISC3)) {
+                                      DR_MATCHER_CRITERIA_MISC3 |
+                                      DR_MATCHER_CRITERIA_MISC5)) {
                inner = false;
 
                if (dr_mask_is_wqe_metadata_set(&mask.misc2))
@@ -528,6 +535,9 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher,
                        if (dr_mask_is_tnl_gtpu(&mask, dmn))
                                mlx5dr_ste_build_tnl_gtpu(ste_ctx, &sb[idx++],
                                                          &mask, inner, rx);
+               } else if (dr_mask_is_tnl_header_0_1_set(&mask.misc5)) {
+                       mlx5dr_ste_build_tnl_header_0_1(ste_ctx, &sb[idx++],
+                                                       &mask, inner, rx);
                }
 
                if (DR_MASK_IS_ETH_L4_MISC_SET(mask.misc3, outer))
index 9bf25231c9c96923556dfec9f8ed3f55cc3127cd..67094dba233cc998b8623eef7f3d9d3fdfbe377c 100644 (file)
@@ -1303,6 +1303,16 @@ void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx,
        ste_ctx->build_flex_parser_1_init(sb, mask);
 }
 
+void mlx5dr_ste_build_tnl_header_0_1(struct mlx5dr_ste_ctx *ste_ctx,
+                                    struct mlx5dr_ste_build *sb,
+                                    struct mlx5dr_match_param *mask,
+                                    bool inner, bool rx)
+{
+       sb->rx = rx;
+       sb->inner = inner;
+       ste_ctx->build_tnl_header_0_1_init(sb, mask);
+}
+
 static struct mlx5dr_ste_ctx *mlx5dr_ste_ctx_arr[] = {
        [MLX5_STEERING_FORMAT_CONNECTX_5] = &ste_ctx_v0,
        [MLX5_STEERING_FORMAT_CONNECTX_6DX] = &ste_ctx_v1,
index 2d52d065dc8be33ced768f06fe2462543c55b10c..e6c25bdf0da02f99343ed2933fe77266dd20ec20 100644 (file)
@@ -141,6 +141,7 @@ struct mlx5dr_ste_ctx {
        void DR_STE_CTX_BUILDER(flex_parser_0);
        void DR_STE_CTX_BUILDER(flex_parser_1);
        void DR_STE_CTX_BUILDER(tnl_gtpu);
+       void DR_STE_CTX_BUILDER(tnl_header_0_1);
        void DR_STE_CTX_BUILDER(tnl_gtpu_flex_parser_0);
        void DR_STE_CTX_BUILDER(tnl_gtpu_flex_parser_1);
 
index 17bfd1ec058962902ba4caeac1497158354f5279..2d62950f7a294bc461bbe2e32885462884148ab9 100644 (file)
@@ -80,6 +80,7 @@ enum {
        DR_STE_V0_LU_TYPE_GENERAL_PURPOSE               = 0x18,
        DR_STE_V0_LU_TYPE_STEERING_REGISTERS_0          = 0x2f,
        DR_STE_V0_LU_TYPE_STEERING_REGISTERS_1          = 0x30,
+       DR_STE_V0_LU_TYPE_TUNNEL_HEADER                 = 0x34,
        DR_STE_V0_LU_TYPE_DONT_CARE                     = MLX5DR_STE_LU_TYPE_DONT_CARE,
 };
 
@@ -1875,6 +1876,27 @@ dr_ste_v0_build_tnl_gtpu_flex_parser_1_init(struct mlx5dr_ste_build *sb,
        sb->ste_build_tag_func = &dr_ste_v0_build_tnl_gtpu_flex_parser_1_tag;
 }
 
+static int dr_ste_v0_build_tnl_header_0_1_tag(struct mlx5dr_match_param *value,
+                                             struct mlx5dr_ste_build *sb,
+                                             uint8_t *tag)
+{
+       struct mlx5dr_match_misc5 *misc5 = &value->misc5;
+
+       DR_STE_SET_TAG(tunnel_header, tag, tunnel_header_0, misc5, tunnel_header_0);
+       DR_STE_SET_TAG(tunnel_header, tag, tunnel_header_1, misc5, tunnel_header_1);
+
+       return 0;
+}
+
+static void dr_ste_v0_build_tnl_header_0_1_init(struct mlx5dr_ste_build *sb,
+                                               struct mlx5dr_match_param *mask)
+{
+       sb->lu_type = DR_STE_V0_LU_TYPE_TUNNEL_HEADER;
+       dr_ste_v0_build_tnl_header_0_1_tag(mask, sb, sb->bit_mask);
+       sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
+       sb->ste_build_tag_func = &dr_ste_v0_build_tnl_header_0_1_tag;
+}
+
 struct mlx5dr_ste_ctx ste_ctx_v0 = {
        /* Builders */
        .build_eth_l2_src_dst_init      = &dr_ste_v0_build_eth_l2_src_dst_init,
@@ -1903,6 +1925,7 @@ struct mlx5dr_ste_ctx ste_ctx_v0 = {
        .build_flex_parser_0_init       = &dr_ste_v0_build_flex_parser_0_init,
        .build_flex_parser_1_init       = &dr_ste_v0_build_flex_parser_1_init,
        .build_tnl_gtpu_init            = &dr_ste_v0_build_flex_parser_tnl_gtpu_init,
+       .build_tnl_header_0_1_init      = &dr_ste_v0_build_tnl_header_0_1_init,
        .build_tnl_gtpu_flex_parser_0_init   = &dr_ste_v0_build_tnl_gtpu_flex_parser_0_init,
        .build_tnl_gtpu_flex_parser_1_init   = &dr_ste_v0_build_tnl_gtpu_flex_parser_1_init,
 
index a7772804f8e59fdfe986d07cace4245369ad22b7..9c72be2c2b6b3357f04bd4a621c7e420f8af09c4 100644 (file)
@@ -1713,6 +1713,27 @@ dr_ste_v1_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb,
        sb->ste_build_tag_func = &dr_ste_v1_build_flex_parser_tnl_geneve_tag;
 }
 
+static int dr_ste_v1_build_tnl_header_0_1_tag(struct mlx5dr_match_param *value,
+                                             struct mlx5dr_ste_build *sb,
+                                             uint8_t *tag)
+{
+       struct mlx5dr_match_misc5 *misc5 = &value->misc5;
+
+       DR_STE_SET_TAG(tunnel_header, tag, tunnel_header_0, misc5, tunnel_header_0);
+       DR_STE_SET_TAG(tunnel_header, tag, tunnel_header_1, misc5, tunnel_header_1);
+
+       return 0;
+}
+
+static void dr_ste_v1_build_tnl_header_0_1_init(struct mlx5dr_ste_build *sb,
+                                               struct mlx5dr_match_param *mask)
+{
+       sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER;
+       dr_ste_v1_build_tnl_header_0_1_tag(mask, sb, sb->bit_mask);
+       sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
+       sb->ste_build_tag_func = &dr_ste_v1_build_tnl_header_0_1_tag;
+}
+
 static int dr_ste_v1_build_register_0_tag(struct mlx5dr_match_param *value,
                                          struct mlx5dr_ste_build *sb,
                                          u8 *tag)
@@ -2026,6 +2047,7 @@ struct mlx5dr_ste_ctx ste_ctx_v1 = {
        .build_flex_parser_0_init       = &dr_ste_v1_build_flex_parser_0_init,
        .build_flex_parser_1_init       = &dr_ste_v1_build_flex_parser_1_init,
        .build_tnl_gtpu_init            = &dr_ste_v1_build_flex_parser_tnl_gtpu_init,
+       .build_tnl_header_0_1_init      = &dr_ste_v1_build_tnl_header_0_1_init,
        .build_tnl_gtpu_flex_parser_0_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_0_init,
        .build_tnl_gtpu_flex_parser_1_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_1_init,
 
index b4987822a81a49ed04aba03c26893450a93438e6..5805e2554a5933ef107ebfd5f82160b199aae511 100644 (file)
@@ -456,6 +456,10 @@ void mlx5dr_ste_build_tnl_gtpu_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx,
                                             struct mlx5dr_match_param *mask,
                                             struct mlx5dr_cmd_caps *caps,
                                             bool inner, bool rx);
+void mlx5dr_ste_build_tnl_header_0_1(struct mlx5dr_ste_ctx *ste_ctx,
+                                    struct mlx5dr_ste_build *sb,
+                                    struct mlx5dr_match_param *mask,
+                                    bool inner, bool rx);
 void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx,
                                      struct mlx5dr_ste_build *sb,
                                      struct mlx5dr_match_param *mask,
index d2a937f697841c05a85f0269d5e2803be9831107..d0e20bda2622050f77ad9662f4f01d9efbe158ff 100644 (file)
@@ -490,6 +490,14 @@ struct mlx5_ifc_ste_flex_parser_tnl_gtpu_bits {
        u8         reserved_at_40[0x40];
 };
 
+struct mlx5_ifc_ste_tunnel_header_bits {
+       u8         tunnel_header_0[0x20];
+
+       u8         tunnel_header_1[0x20];
+
+       u8         reserved_at_40[0x40];
+};
+
 struct mlx5_ifc_ste_general_purpose_bits {
        u8         general_purpose_lookup_field[0x20];