arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs

This SoC has a DMA controller with tx/rx channels for all of the
UART controller IPs: add the apdma node and wire up the DMAs on
all controllers.
When one of the UART controllers is used as a serial console,
the DMA will be automatically ignored.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221027095504.37432-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 34e1f10..ae2eaad 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -316,6 +316,8 @@
                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
                        clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
                        clock-names = "baud", "bus";
+                       dmas = <&apdma 0>, <&apdma 1>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
 
@@ -326,9 +328,37 @@
                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
                        clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
                        clock-names = "baud", "bus";
+                       dmas = <&apdma 2>, <&apdma 3>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
 
+               apdma: dma-controller@11000380 {
+                       compatible = "mediatek,mt6795-uart-dma",
+                                    "mediatek,mt6577-uart-dma";
+                       reg = <0 0x11000380 0 0x60>,
+                             <0 0x11000400 0 0x60>,
+                             <0 0x11000480 0 0x60>,
+                             <0 0x11000500 0 0x60>,
+                             <0 0x11000580 0 0x60>,
+                             <0 0x11000600 0 0x60>,
+                             <0 0x11000680 0 0x60>,
+                             <0 0x11000700 0 0x60>;
+                       interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
+                                    <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
+                                    <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
+                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
+                                    <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
+                                    <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
+                                    <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+                       dma-requests = <8>;
+                       clocks = <&pericfg CLK_PERI_AP_DMA>;
+                       clock-names = "apdma";
+                       mediatek,dma-33bits;
+                       #dma-cells = <1>;
+               };
+
                uart2: serial@11004000 {
                        compatible = "mediatek,mt6795-uart",
                                     "mediatek,mt6577-uart";
@@ -336,6 +366,8 @@
                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
                        clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
                        clock-names = "baud", "bus";
+                       dmas = <&apdma 4>, <&apdma 5>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
 
@@ -346,6 +378,8 @@
                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
                        clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
                        clock-names = "baud", "bus";
+                       dmas = <&apdma 6>, <&apdma 7>;
+                       dma-names = "tx", "rx";
                        status = "disabled";
                };
        };