[NFC][InstCombine] Revisit shift-by-signext tests

llvm-svn: 373055

diff --git a/llvm/test/Transforms/InstCombine/shift-by-signext.ll b/llvm/test/Transforms/InstCombine/shift-by-signext.ll
index dab37a4..9d6cf90 100644 (file)
--- a/llvm/test/Transforms/InstCombine/shift-by-signext.ll
+++ b/llvm/test/Transforms/InstCombine/shift-by-signext.ll
@@ -66,33 +66,79 @@ define <2 x i32> @t5_vec_ashr(<2 x i32> %x, <2 x i8> %shamt) {
   ret <2 x i32> %r
 }
 
-; This is not valid for funnel shifts
-declare i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
-declare i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
-define i32 @n6_fshl(i32 %x, i32 %y, i8 %shamt) {
-; CHECK-LABEL: @n6_fshl(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[SHAMT_WIDE1]])
+define i32 @t6_twoshifts(i32 %x, i8 %shamt) {
+; CHECK-LABEL: @t6_twoshifts(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[SHAMT_WIDE:%.*]] = sext i8 [[SHAMT:%.*]] to i32
+; CHECK-NEXT:    br label [[WORK:%.*]]
+; CHECK:       work:
+; CHECK-NEXT:    br label [[END:%.*]]
+; CHECK:       end:
+; CHECK-NEXT:    [[N0:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[N0]], [[SHAMT_WIDE]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
+bb:
   %shamt_wide = sext i8 %shamt to i32
-  %r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %shamt_wide)
+  br label %work
+work:
+  %n0 = shl i32 %x, %shamt_wide
+  %r = ashr i32 %n0, %shamt_wide
+  br label %end
+end:
   ret i32 %r
 }
-define i32 @n7_fshr(i32 %x, i32 %y, i8 %shamt) {
-; CHECK-LABEL: @n7_fshr(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.fshr.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[SHAMT_WIDE1]])
-; CHECK-NEXT:    ret i32 [[R]]
+
+; This is not valid for funnel shifts in general
+declare i7 @llvm.fshl.i7(i7 %a, i7 %b, i7 %c)
+declare i7 @llvm.fshr.i7(i7 %a, i7 %b, i7 %c)
+define i7 @n7_fshl(i7 %x, i7 %y, i6 %shamt) {
+; CHECK-LABEL: @n7_fshl(
+; CHECK-NEXT:    [[SHAMT_WIDE:%.*]] = sext i6 [[SHAMT:%.*]] to i7
+; CHECK-NEXT:    [[R:%.*]] = call i7 @llvm.fshl.i7(i7 [[X:%.*]], i7 [[Y:%.*]], i7 [[SHAMT_WIDE]])
+; CHECK-NEXT:    ret i7 [[R]]
 ;
-  %shamt_wide = sext i8 %shamt to i32
-  %r = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %shamt_wide)
-  ret i32 %r
+  %shamt_wide = sext i6 %shamt to i7
+  %r = call i7 @llvm.fshl.i7(i7 %x, i7 %y, i7 %shamt_wide)
+  ret i7 %r
+}
+define i7 @n8_fshr(i7 %x, i7 %y, i6 %shamt) {
+; CHECK-LABEL: @n8_fshr(
+; CHECK-NEXT:    [[SHAMT_WIDE:%.*]] = sext i6 [[SHAMT:%.*]] to i7
+; CHECK-NEXT:    [[R:%.*]] = call i7 @llvm.fshr.i7(i7 [[X:%.*]], i7 [[Y:%.*]], i7 [[SHAMT_WIDE]])
+; CHECK-NEXT:    ret i7 [[R]]
+;
+  %shamt_wide = sext i6 %shamt to i7
+  %r = call i7 @llvm.fshr.i7(i7 %x, i7 %y, i7 %shamt_wide)
+  ret i7 %r
+}
+; And the cases that are safe are handled by SimplifyDemandedBits().
+declare i8 @llvm.fshl.i8(i8 %a, i8 %b, i8 %c)
+declare i8 @llvm.fshr.i8(i8 %a, i8 %b, i8 %c)
+define i8 @t9_fshl(i8 %x, i8 %y, i6 %shamt) {
+; CHECK-LABEL: @t9_fshl(
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext i6 [[SHAMT:%.*]] to i8
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.fshl.i8(i8 [[X:%.*]], i8 [[Y:%.*]], i8 [[SHAMT_WIDE1]])
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %shamt_wide = sext i6 %shamt to i8
+  %r = call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 %shamt_wide)
+  ret i8 %r
+}
+define i8 @t10_fshr(i8 %x, i8 %y, i6 %shamt) {
+; CHECK-LABEL: @t10_fshr(
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext i6 [[SHAMT:%.*]] to i8
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[Y:%.*]], i8 [[SHAMT_WIDE1]])
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %shamt_wide = sext i6 %shamt to i8
+  %r = call i8 @llvm.fshr.i8(i8 %x, i8 %y, i8 %shamt_wide)
+  ret i8 %r
 }
 
 declare void @use32(i32)
-define i32 @n8_extrause(i32 %x, i8 %shamt) {
-; CHECK-LABEL: @n8_extrause(
+define i32 @n11_extrause(i32 %x, i8 %shamt) {
+; CHECK-LABEL: @n11_extrause(
 ; CHECK-NEXT:    [[SHAMT_WIDE:%.*]] = sext i8 [[SHAMT:%.*]] to i32
 ; CHECK-NEXT:    call void @use32(i32 [[SHAMT_WIDE]])
 ; CHECK-NEXT:    [[R:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE]]
@@ -103,3 +149,25 @@ define i32 @n8_extrause(i32 %x, i8 %shamt) {
   %r = shl i32 %x, %shamt_wide
   ret i32 %r
 }
+define i32 @n12_twoshifts_and_extrause(i32 %x, i8 %shamt) {
+; CHECK-LABEL: @n12_twoshifts_and_extrause(
+; CHECK-NEXT:    [[SHAMT_WIDE:%.*]] = sext i8 [[SHAMT:%.*]] to i32
+; CHECK-NEXT:    br label [[WORK:%.*]]
+; CHECK:       work:
+; CHECK-NEXT:    br label [[END:%.*]]
+; CHECK:       end:
+; CHECK-NEXT:    [[N0:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[N0]], [[SHAMT_WIDE]]
+; CHECK-NEXT:    call void @use32(i32 [[SHAMT_WIDE]])
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %shamt_wide = sext i8 %shamt to i32
+  br label %work
+work:
+  %n0 = shl i32 %x, %shamt_wide
+  %r = ashr i32 %n0, %shamt_wide
+  br label %end
+end:
+  call void @use32(i32 %shamt_wide)
+  ret i32 %r
+}