struct uart_port *port = dev_id;
struct clps711x_port *s = dev_get_drvdata(port->dev);
unsigned int status, flg;
- u32 sysflg;
u16 ch;
for (;;) {
+ u32 sysflg = 0;
+
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
if (sysflg & SYSFLG_URXFE)
break;
- ch = readw_relaxed(port->membase + UARTDR_OFFSET);
+ ch = readw(port->membase + UARTDR_OFFSET);
status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
ch &= 0xff;
struct uart_port *port = dev_id;
struct clps711x_port *s = dev_get_drvdata(port->dev);
struct circ_buf *xmit = &port->state->xmit;
- u32 sysflg;
if (port->x_char) {
- writew_relaxed(port->x_char, port->membase + UARTDR_OFFSET);
+ writew(port->x_char, port->membase + UARTDR_OFFSET);
port->icount.tx++;
port->x_char = 0;
return IRQ_HANDLED;
}
while (!uart_circ_empty(xmit)) {
- writew_relaxed(xmit->buf[xmit->tail],
- port->membase + UARTDR_OFFSET);
+ u32 sysflg = 0;
+
+ writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
- u32 sysflg;
+ u32 sysflg = 0;
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
unsigned int result = 0;
- u32 sysflg;
if (s->use_ms) {
+ u32 sysflg = 0;
+
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
if (sysflg & SYSFLG1_DCD)
result |= TIOCM_CAR;
{
unsigned int ubrlcr;
- ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET);
+ ubrlcr = readl(port->membase + UBRLCR_OFFSET);
if (break_state)
ubrlcr |= UBRLCR_BREAK;
else
ubrlcr &= ~UBRLCR_BREAK;
- writel_relaxed(ubrlcr, port->membase + UBRLCR_OFFSET);
+ writel(ubrlcr, port->membase + UBRLCR_OFFSET);
}
static void uart_clps711x_set_ldisc(struct uart_port *port, int ld)
struct clps711x_port *s = dev_get_drvdata(port->dev);
/* Disable break */
- writel_relaxed(readl_relaxed(port->membase + UBRLCR_OFFSET) &
- ~UBRLCR_BREAK, port->membase + UBRLCR_OFFSET);
+ writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
+ port->membase + UBRLCR_OFFSET);
/* Enable the port */
return regmap_update_bits(s->syscon, SYSCON_OFFSET,
uart_update_timeout(port, termios->c_cflag, baud);
- writel_relaxed(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
+ writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
}
static const char *uart_clps711x_type(struct uart_port *port)
static void uart_clps711x_console_putchar(struct uart_port *port, int ch)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
- u32 sysflg;
+ u32 sysflg = 0;
do {
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
} while (sysflg & SYSFLG_UTXFF);
- writew_relaxed(ch, port->membase + UARTDR_OFFSET);
+ writew(ch, port->membase + UARTDR_OFFSET);
}
static void uart_clps711x_console_write(struct console *co, const char *c,
{
struct uart_port *port = clps711x_uart.state[co->index].uart_port;
struct clps711x_port *s = dev_get_drvdata(port->dev);
- u32 sysflg;
+ u32 sysflg = 0;
uart_console_write(port, c, n, uart_clps711x_console_putchar);
int ret, index = co->index;
struct clps711x_port *s;
struct uart_port *port;
- u32 ubrlcr, syscon;
unsigned int quot;
+ u32 ubrlcr;
if (index < 0 || index >= UART_CLPS711X_NR)
return -EINVAL;
s = dev_get_drvdata(port->dev);
if (!options) {
+ u32 syscon = 0;
+
regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
if (syscon & SYSCON_UARTEN) {
- ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET);
+ ubrlcr = readl(port->membase + UBRLCR_OFFSET);
if (ubrlcr & UBRLCR_PRTEN) {
if (ubrlcr & UBRLCR_EVENPRT)