ret i64 %or
}
-define i32 @rori_i32(i32 %a) nounwind {
-; RV32I-LABEL: rori_i32:
+define i32 @rori_i32_fshl(i32 %a) nounwind {
+; RV32I-LABEL: rori_i32_fshl:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: slli a0, a0, 31
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32IB-LABEL: rori_i32:
+; RV32IB-LABEL: rori_i32_fshl:
; RV32IB: # %bb.0:
; RV32IB-NEXT: rori a0, a0, 1
; RV32IB-NEXT: ret
;
-; RV32IBB-LABEL: rori_i32:
+; RV32IBB-LABEL: rori_i32_fshl:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: rori a0, a0, 1
; RV32IBB-NEXT: ret
;
-; RV32IBP-LABEL: rori_i32:
+; RV32IBP-LABEL: rori_i32_fshl:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: rori a0, a0, 1
; RV32IBP-NEXT: ret
ret i32 %1
}
+define i32 @rori_i32_fshr(i32 %a) nounwind {
+; RV32I-LABEL: rori_i32_fshr:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 1
+; RV32I-NEXT: srli a0, a0, 31
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: rori_i32_fshr:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 31
+; RV32IB-NEXT: ror a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: rori_i32_fshr:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: addi a1, zero, 31
+; RV32IBB-NEXT: ror a0, a0, a1
+; RV32IBB-NEXT: ret
+;
+; RV32IBP-LABEL: rori_i32_fshr:
+; RV32IBP: # %bb.0:
+; RV32IBP-NEXT: addi a1, zero, 31
+; RV32IBP-NEXT: ror a0, a0, a1
+; RV32IBP-NEXT: ret
+ %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
+ ret i32 %1
+}
+
define i64 @rori_i64(i64 %a) nounwind {
; RV32I-LABEL: rori_i64:
; RV32I: # %bb.0:
ret i64 %1
}
+define i64 @rori_i64_fshr(i64 %a) nounwind {
+; RV32I-LABEL: rori_i64_fshr:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a2, a0, 1
+; RV32I-NEXT: srli a3, a1, 31
+; RV32I-NEXT: or a2, a3, a2
+; RV32I-NEXT: srli a0, a0, 31
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: or a1, a1, a0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: rori_i64_fshr:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a3, zero, 1
+; RV32IB-NEXT: fsl a2, a0, a3, a1
+; RV32IB-NEXT: fsl a1, a1, a3, a0
+; RV32IB-NEXT: mv a0, a2
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: rori_i64_fshr:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: slli a2, a0, 1
+; RV32IBB-NEXT: srli a3, a1, 31
+; RV32IBB-NEXT: or a2, a3, a2
+; RV32IBB-NEXT: srli a0, a0, 31
+; RV32IBB-NEXT: slli a1, a1, 1
+; RV32IBB-NEXT: or a1, a1, a0
+; RV32IBB-NEXT: mv a0, a2
+; RV32IBB-NEXT: ret
+;
+; RV32IBP-LABEL: rori_i64_fshr:
+; RV32IBP: # %bb.0:
+; RV32IBP-NEXT: slli a2, a0, 1
+; RV32IBP-NEXT: srli a3, a1, 31
+; RV32IBP-NEXT: or a2, a3, a2
+; RV32IBP-NEXT: srli a0, a0, 31
+; RV32IBP-NEXT: slli a1, a1, 1
+; RV32IBP-NEXT: or a1, a1, a0
+; RV32IBP-NEXT: mv a0, a2
+; RV32IBP-NEXT: ret
+ %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
+ ret i64 %1
+}
+
define i32 @pack_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: pack_i32:
; RV32I: # %bb.0:
ret i64 %or
}
-define signext i32 @rori_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: rori_i32:
+define signext i32 @rori_i32_fshl(i32 signext %a) nounwind {
+; RV64I-LABEL: rori_i32_fshl:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: slli a0, a0, 31
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64IB-LABEL: rori_i32:
+; RV64IB-LABEL: rori_i32_fshl:
; RV64IB: # %bb.0:
; RV64IB-NEXT: roriw a0, a0, 1
; RV64IB-NEXT: ret
;
-; RV64IBB-LABEL: rori_i32:
+; RV64IBB-LABEL: rori_i32_fshl:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: roriw a0, a0, 1
; RV64IBB-NEXT: ret
;
-; RV64IBP-LABEL: rori_i32:
+; RV64IBP-LABEL: rori_i32_fshl:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: roriw a0, a0, 1
; RV64IBP-NEXT: ret
ret i32 %1
}
-define i64 @rori_i64(i64 %a) nounwind {
-; RV64I-LABEL: rori_i64:
+define signext i32 @rori_i32_fshr(i32 signext %a) nounwind {
+; RV64I-LABEL: rori_i32_fshr:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 1
+; RV64I-NEXT: srliw a0, a0, 31
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: rori_i32_fshr:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: slli a1, a0, 1
+; RV64IB-NEXT: srliw a0, a0, 31
+; RV64IB-NEXT: or a0, a0, a1
+; RV64IB-NEXT: sext.w a0, a0
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: rori_i32_fshr:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: slli a1, a0, 1
+; RV64IBB-NEXT: srliw a0, a0, 31
+; RV64IBB-NEXT: or a0, a0, a1
+; RV64IBB-NEXT: sext.w a0, a0
+; RV64IBB-NEXT: ret
+;
+; RV64IBP-LABEL: rori_i32_fshr:
+; RV64IBP: # %bb.0:
+; RV64IBP-NEXT: slli a1, a0, 1
+; RV64IBP-NEXT: srliw a0, a0, 31
+; RV64IBP-NEXT: or a0, a0, a1
+; RV64IBP-NEXT: sext.w a0, a0
+; RV64IBP-NEXT: ret
+ %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
+ ret i32 %1
+}
+
+define i64 @rori_i64_fshl(i64 %a) nounwind {
+; RV64I-LABEL: rori_i64_fshl:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64IB-LABEL: rori_i64:
+; RV64IB-LABEL: rori_i64_fshl:
; RV64IB: # %bb.0:
; RV64IB-NEXT: rori a0, a0, 1
; RV64IB-NEXT: ret
;
-; RV64IBB-LABEL: rori_i64:
+; RV64IBB-LABEL: rori_i64_fshl:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: rori a0, a0, 1
; RV64IBB-NEXT: ret
;
-; RV64IBP-LABEL: rori_i64:
+; RV64IBP-LABEL: rori_i64_fshl:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: rori a0, a0, 1
; RV64IBP-NEXT: ret
ret i64 %1
}
+define i64 @rori_i64_fshr(i64 %a) nounwind {
+; RV64I-LABEL: rori_i64_fshr:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a0, 1
+; RV64I-NEXT: srli a0, a0, 63
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: rori_i64_fshr:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 63
+; RV64IB-NEXT: ror a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: rori_i64_fshr:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: addi a1, zero, 63
+; RV64IBB-NEXT: ror a0, a0, a1
+; RV64IBB-NEXT: ret
+;
+; RV64IBP-LABEL: rori_i64_fshr:
+; RV64IBP: # %bb.0:
+; RV64IBP-NEXT: addi a1, zero, 63
+; RV64IBP-NEXT: ror a0, a0, a1
+; RV64IBP-NEXT: ret
+ %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
+ ret i64 %1
+}
+
define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: pack_i32:
; RV64I: # %bb.0: