.get_data = catu_get_data_etr_buf,
};
-coresight_simple_reg32(devid, CORESIGHT_DEVID);
-coresight_simple_reg32(control, CATU_CONTROL);
-coresight_simple_reg32(status, CATU_STATUS);
-coresight_simple_reg32(mode, CATU_MODE);
-coresight_simple_reg32(axictrl, CATU_AXICTRL);
-coresight_simple_reg32(irqen, CATU_IRQEN);
-coresight_simple_reg64(sladdr, CATU_SLADDRLO, CATU_SLADDRHI);
-coresight_simple_reg64(inaddr, CATU_INADDRLO, CATU_INADDRHI);
-
static struct attribute *catu_mgmt_attrs[] = {
- &dev_attr_devid.attr,
- &dev_attr_control.attr,
- &dev_attr_status.attr,
- &dev_attr_mode.attr,
- &dev_attr_axictrl.attr,
- &dev_attr_irqen.attr,
- &dev_attr_sladdr.attr,
- &dev_attr_inaddr.attr,
+ coresight_simple_reg32(devid, CORESIGHT_DEVID),
+ coresight_simple_reg32(control, CATU_CONTROL),
+ coresight_simple_reg32(status, CATU_STATUS),
+ coresight_simple_reg32(mode, CATU_MODE),
+ coresight_simple_reg32(axictrl, CATU_AXICTRL),
+ coresight_simple_reg32(irqen, CATU_IRQEN),
+ coresight_simple_reg64(sladdr, CATU_SLADDRLO, CATU_SLADDRHI),
+ coresight_simple_reg64(inaddr, CATU_INADDRLO, CATU_INADDRHI),
NULL,
};
static const struct cti_assoc_op *cti_assoc_ops;
+ssize_t coresight_simple_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct coresight_device *csdev = container_of(_dev, struct coresight_device, dev);
+ struct cs_pair_attribute *cs_attr = container_of(attr, struct cs_pair_attribute, attr);
+ u64 val;
+
+ pm_runtime_get_sync(_dev->parent);
+ val = csdev_access_relaxed_read_pair(&csdev->access, cs_attr->lo_off, cs_attr->hi_off);
+ pm_runtime_put_sync(_dev->parent);
+ return sysfs_emit(buf, "0x%llx\n", val);
+}
+EXPORT_SYMBOL_GPL(coresight_simple_show);
+
void coresight_set_cti_ops(const struct cti_assoc_op *cti_op)
{
cti_assoc_ops = cti_op;
.llseek = no_llseek,
};
-coresight_simple_reg32(rdp, ETB_RAM_DEPTH_REG);
-coresight_simple_reg32(sts, ETB_STATUS_REG);
-coresight_simple_reg32(rrp, ETB_RAM_READ_POINTER);
-coresight_simple_reg32(rwp, ETB_RAM_WRITE_POINTER);
-coresight_simple_reg32(trg, ETB_TRG);
-coresight_simple_reg32(ctl, ETB_CTL_REG);
-coresight_simple_reg32(ffsr, ETB_FFSR);
-coresight_simple_reg32(ffcr, ETB_FFCR);
-
static struct attribute *coresight_etb_mgmt_attrs[] = {
- &dev_attr_rdp.attr,
- &dev_attr_sts.attr,
- &dev_attr_rrp.attr,
- &dev_attr_rwp.attr,
- &dev_attr_trg.attr,
- &dev_attr_ctl.attr,
- &dev_attr_ffsr.attr,
- &dev_attr_ffcr.attr,
+ coresight_simple_reg32(rdp, ETB_RAM_DEPTH_REG),
+ coresight_simple_reg32(sts, ETB_STATUS_REG),
+ coresight_simple_reg32(rrp, ETB_RAM_READ_POINTER),
+ coresight_simple_reg32(rwp, ETB_RAM_WRITE_POINTER),
+ coresight_simple_reg32(trg, ETB_TRG),
+ coresight_simple_reg32(ctl, ETB_CTL_REG),
+ coresight_simple_reg32(ffsr, ETB_FFSR),
+ coresight_simple_reg32(ffcr, ETB_FFCR),
NULL,
};
NULL,
};
-coresight_simple_reg32(etmccr, ETMCCR);
-coresight_simple_reg32(etmccer, ETMCCER);
-coresight_simple_reg32(etmscr, ETMSCR);
-coresight_simple_reg32(etmidr, ETMIDR);
-coresight_simple_reg32(etmcr, ETMCR);
-coresight_simple_reg32(etmtraceidr, ETMTRACEIDR);
-coresight_simple_reg32(etmteevr, ETMTEEVR);
-coresight_simple_reg32(etmtssvr, ETMTSSCR);
-coresight_simple_reg32(etmtecr1, ETMTECR1);
-coresight_simple_reg32(etmtecr2, ETMTECR2);
-
static struct attribute *coresight_etm_mgmt_attrs[] = {
- &dev_attr_etmccr.attr,
- &dev_attr_etmccer.attr,
- &dev_attr_etmscr.attr,
- &dev_attr_etmidr.attr,
- &dev_attr_etmcr.attr,
- &dev_attr_etmtraceidr.attr,
- &dev_attr_etmteevr.attr,
- &dev_attr_etmtssvr.attr,
- &dev_attr_etmtecr1.attr,
- &dev_attr_etmtecr2.attr,
+ coresight_simple_reg32(etmccr, ETMCCR),
+ coresight_simple_reg32(etmccer, ETMCCER),
+ coresight_simple_reg32(etmscr, ETMSCR),
+ coresight_simple_reg32(etmidr, ETMIDR),
+ coresight_simple_reg32(etmcr, ETMCR),
+ coresight_simple_reg32(etmtraceidr, ETMTRACEIDR),
+ coresight_simple_reg32(etmteevr, ETMTEEVR),
+ coresight_simple_reg32(etmtssvr, ETMTSSCR),
+ coresight_simple_reg32(etmtecr1, ETMTECR1),
+ coresight_simple_reg32(etmtecr2, ETMTECR2),
NULL,
};
#define ETM_MODE_EXCL_KERN BIT(30)
#define ETM_MODE_EXCL_USER BIT(31)
+struct cs_pair_attribute {
+ struct device_attribute attr;
+ s32 lo_off;
+ s32 hi_off;
+};
-#define __coresight_simple_show(name, lo_off, hi_off) \
-static ssize_t name##_show(struct device *_dev, \
- struct device_attribute *attr, char *buf) \
-{ \
- struct coresight_device *csdev = container_of(_dev, struct coresight_device, dev); \
- u64 val; \
- pm_runtime_get_sync(_dev->parent); \
- val = csdev_access_relaxed_read_pair(&csdev->access, lo_off, hi_off); \
- pm_runtime_put_sync(_dev->parent); \
- return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \
-} \
-static DEVICE_ATTR_RO(name)
-
-#define coresight_simple_reg32(name, offset) \
- __coresight_simple_show(name, offset, -1)
-#define coresight_simple_reg64(name, lo_off, hi_off) \
- __coresight_simple_show(name, lo_off, hi_off)
+extern ssize_t coresight_simple_show(struct device *_dev,
+ struct device_attribute *attr, char *buf);
+
+#define coresight_simple_reg32(name, offset) \
+ (&((struct cs_pair_attribute[]) { \
+ { \
+ __ATTR(name, 0444, coresight_simple_show, NULL), \
+ offset, -1 \
+ } \
+ })[0].attr.attr)
+
+#define coresight_simple_reg64(name, lo_off, hi_off) \
+ (&((struct cs_pair_attribute[]) { \
+ { \
+ __ATTR(name, 0444, coresight_simple_show, NULL), \
+ lo_off, hi_off \
+ } \
+ })[0].attr.attr)
extern const u32 coresight_barrier_pkt[4];
#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
.link_ops = &replicator_link_ops,
};
-coresight_simple_reg32(idfilter0, REPLICATOR_IDFILTER0);
-coresight_simple_reg32(idfilter1, REPLICATOR_IDFILTER1);
-
static struct attribute *replicator_mgmt_attrs[] = {
- &dev_attr_idfilter0.attr,
- &dev_attr_idfilter1.attr,
+ coresight_simple_reg32(idfilter0, REPLICATOR_IDFILTER0),
+ coresight_simple_reg32(idfilter1, REPLICATOR_IDFILTER1),
NULL,
};
}
static DEVICE_ATTR_RW(traceid);
-coresight_simple_reg32(tcsr, STMTCSR);
-coresight_simple_reg32(tsfreqr, STMTSFREQR);
-coresight_simple_reg32(syncr, STMSYNCR);
-coresight_simple_reg32(sper, STMSPER);
-coresight_simple_reg32(spter, STMSPTER);
-coresight_simple_reg32(privmaskr, STMPRIVMASKR);
-coresight_simple_reg32(spscr, STMSPSCR);
-coresight_simple_reg32(spmscr, STMSPMSCR);
-coresight_simple_reg32(spfeat1r, STMSPFEAT1R);
-coresight_simple_reg32(spfeat2r, STMSPFEAT2R);
-coresight_simple_reg32(spfeat3r, STMSPFEAT3R);
-coresight_simple_reg32(devid, CORESIGHT_DEVID);
-
static struct attribute *coresight_stm_attrs[] = {
&dev_attr_hwevent_enable.attr,
&dev_attr_hwevent_select.attr,
};
static struct attribute *coresight_stm_mgmt_attrs[] = {
- &dev_attr_tcsr.attr,
- &dev_attr_tsfreqr.attr,
- &dev_attr_syncr.attr,
- &dev_attr_sper.attr,
- &dev_attr_spter.attr,
- &dev_attr_privmaskr.attr,
- &dev_attr_spscr.attr,
- &dev_attr_spmscr.attr,
- &dev_attr_spfeat1r.attr,
- &dev_attr_spfeat2r.attr,
- &dev_attr_spfeat3r.attr,
- &dev_attr_devid.attr,
+ coresight_simple_reg32(tcsr, STMTCSR),
+ coresight_simple_reg32(tsfreqr, STMTSFREQR),
+ coresight_simple_reg32(syncr, STMSYNCR),
+ coresight_simple_reg32(sper, STMSPER),
+ coresight_simple_reg32(spter, STMSPTER),
+ coresight_simple_reg32(privmaskr, STMPRIVMASKR),
+ coresight_simple_reg32(spscr, STMSPSCR),
+ coresight_simple_reg32(spmscr, STMSPMSCR),
+ coresight_simple_reg32(spfeat1r, STMSPFEAT1R),
+ coresight_simple_reg32(spfeat2r, STMSPFEAT2R),
+ coresight_simple_reg32(spfeat3r, STMSPFEAT3R),
+ coresight_simple_reg32(devid, CORESIGHT_DEVID),
NULL,
};
return memwidth;
}
-coresight_simple_reg32(rsz, TMC_RSZ);
-coresight_simple_reg32(sts, TMC_STS);
-coresight_simple_reg32(trg, TMC_TRG);
-coresight_simple_reg32(ctl, TMC_CTL);
-coresight_simple_reg32(ffsr, TMC_FFSR);
-coresight_simple_reg32(ffcr, TMC_FFCR);
-coresight_simple_reg32(mode, TMC_MODE);
-coresight_simple_reg32(pscr, TMC_PSCR);
-coresight_simple_reg32(axictl, TMC_AXICTL);
-coresight_simple_reg32(authstatus, TMC_AUTHSTATUS);
-coresight_simple_reg32(devid, CORESIGHT_DEVID);
-coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI);
-coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI);
-coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI);
-
static struct attribute *coresight_tmc_mgmt_attrs[] = {
- &dev_attr_rsz.attr,
- &dev_attr_sts.attr,
- &dev_attr_rrp.attr,
- &dev_attr_rwp.attr,
- &dev_attr_trg.attr,
- &dev_attr_ctl.attr,
- &dev_attr_ffsr.attr,
- &dev_attr_ffcr.attr,
- &dev_attr_mode.attr,
- &dev_attr_pscr.attr,
- &dev_attr_devid.attr,
- &dev_attr_dba.attr,
- &dev_attr_axictl.attr,
- &dev_attr_authstatus.attr,
+ coresight_simple_reg32(rsz, TMC_RSZ),
+ coresight_simple_reg32(sts, TMC_STS),
+ coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI),
+ coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI),
+ coresight_simple_reg32(trg, TMC_TRG),
+ coresight_simple_reg32(ctl, TMC_CTL),
+ coresight_simple_reg32(ffsr, TMC_FFSR),
+ coresight_simple_reg32(ffcr, TMC_FFCR),
+ coresight_simple_reg32(mode, TMC_MODE),
+ coresight_simple_reg32(pscr, TMC_PSCR),
+ coresight_simple_reg32(devid, CORESIGHT_DEVID),
+ coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI),
+ coresight_simple_reg32(axictl, TMC_AXICTL),
+ coresight_simple_reg32(authstatus, TMC_AUTHSTATUS),
NULL,
};
projects / platform / kernel / linux-rpi.git / commitdiff