drm/amdgpu: Fix error & warnings in gmc_v9_0.c

Fix below checkpatch error & warnings:

ERROR: that open brace { should be on the previous line

WARNING: static const char * array should probably be static const char * const
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ebdbc82..3f4fa94 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -81,7 +81,7 @@
 
 #define MAX_MEM_RANGES 8
 
-static const char *gfxhub_client_ids[] = {
+static const char * const gfxhub_client_ids[] = {
        "CB",
        "DB",
        "IA",
@@ -332,14 +332,12 @@ static const char *mmhub_client_ids_aldebaran[][2] = {
        [384+0][1] = "OSS",
 };
 
-static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
-{
+static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = {
        SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
        SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 };
 
-static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
-{
+static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = {
        SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
        SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 };
@@ -416,13 +414,14 @@ static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 
 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
                struct amdgpu_irq_src *src,
-               unsigned type,
+               unsigned int type,
                enum amdgpu_interrupt_state state)
 {
        u32 bits, i, tmp, reg;
 
        /* Devices newer then VEGA10/12 shall have these programming
-            sequences performed by PSP BL */
+        * sequences performed by PSP BL
+        */
        if (adev->asic_type >= CHIP_VEGA20)
                return 0;
 
@@ -466,7 +465,7 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 
 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                                        struct amdgpu_irq_src *src,
-                                       unsigned type,
+                                       unsigned int type,
                                        enum amdgpu_interrupt_state state)
 {
        struct amdgpu_vmhub *hub;
@@ -631,8 +630,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
        amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 
        dev_err(adev->dev,
-               "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
-               "pasid:%u, for process %s pid %d thread %s pid %d)\n",
+               "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
                hub_name, retry_fault ? "retry" : "no-retry",
                entry->src_id, entry->ring_id, entry->vmid,
                entry->pasid, task_info.process_name, task_info.tgid,
@@ -816,7 +814,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
                                        uint32_t vmhub, uint32_t flush_type)
 {
        bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
-       const unsigned eng = 17;
+       const unsigned int eng = 17;
        u32 j, inv_req, inv_req2, tmp;
        struct amdgpu_vmhub *hub;
 
@@ -1033,13 +1031,13 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 }
 
 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
-                                           unsigned vmid, uint64_t pd_addr)
+                                           unsigned int vmid, uint64_t pd_addr)
 {
        bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
        struct amdgpu_device *adev = ring->adev;
        struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
        uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
-       unsigned eng = ring->vm_inv_eng;
+       unsigned int eng = ring->vm_inv_eng;
 
        /*
         * It may lose gpuvm invalidate acknowldege state across power-gating
@@ -1081,8 +1079,8 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
        return pd_addr;
 }
 
-static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
-                                       unsigned pasid)
+static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
+                                       unsigned int pasid)
 {
        struct amdgpu_device *adev = ring->adev;
        uint32_t reg;
@@ -1373,10 +1371,10 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
        }
 }
 
-static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
+static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 {
        u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
-       unsigned size;
+       unsigned int size;
 
        /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
 
@@ -2305,7 +2303,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
                return r;
 
        DRM_INFO("PCIE GART of %uM enabled.\n",
-                (unsigned)(adev->gmc.gart_size >> 20));
+                (unsigned int)(adev->gmc.gart_size >> 20));
        if (adev->gmc.pdb0_bo)
                DRM_INFO("PDB0 located at 0x%016llX\n",
                                (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
@@ -2491,8 +2489,7 @@ const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
        .get_clockgating_state = gmc_v9_0_get_clockgating_state,
 };
 
-const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
-{
+const struct amdgpu_ip_block_version gmc_v9_0_ip_block = {
        .type = AMD_IP_BLOCK_TYPE_GMC,
        .major = 9,
        .minor = 0,