PCI: dwc: exynos: Use pci_ops for root config space accessors

Now that DWC drivers can setup their own pci_ops for the root and child
buses, convert the Samsung Exynos driver to use the standard pci_ops for
root bus config accesses.

Link: https://lore.kernel.org/r/20200821035420.380495-11-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: linux-samsung-soc@vger.kernel.org

diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
index 8d82c43ae299845770c704bfca2385b74a3b8c76..242683cde04a5d62e7b19121fea1ed52daadd6c4 100644 (file)
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -336,32 +336,37 @@ static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
        exynos_pcie_sideband_dbi_w_mode(ep, false);
 }
 
-static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
-                               u32 *val)
+static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 *val)
 {
-       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-       struct exynos_pcie *ep = to_exynos_pcie(pci);
-       int ret;
+       struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
 
-       exynos_pcie_sideband_dbi_r_mode(ep, true);
-       ret = dw_pcie_read(pci->dbi_base + where, size, val);
-       exynos_pcie_sideband_dbi_r_mode(ep, false);
-       return ret;
+       if (PCI_SLOT(devfn)) {
+               *val = ~0;
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       }
+
+       *val = dw_pcie_read_dbi(pci, where, size);
+       return PCIBIOS_SUCCESSFUL;
 }
 
-static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
-                               u32 val)
+static int exynos_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 val)
 {
-       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-       struct exynos_pcie *ep = to_exynos_pcie(pci);
-       int ret;
+       struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
 
-       exynos_pcie_sideband_dbi_w_mode(ep, true);
-       ret = dw_pcie_write(pci->dbi_base + where, size, val);
-       exynos_pcie_sideband_dbi_w_mode(ep, false);
-       return ret;
+       if (PCI_SLOT(devfn))
+               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       dw_pcie_write_dbi(pci, where, size, val);
+       return PCIBIOS_SUCCESSFUL;
 }
 
+static struct pci_ops exynos_pci_ops = {
+       .read = exynos_pcie_rd_own_conf,
+       .write = exynos_pcie_wr_own_conf,
+};
+
 static int exynos_pcie_link_up(struct dw_pcie *pci)
 {
        struct exynos_pcie *ep = to_exynos_pcie(pci);
@@ -379,6 +384,8 @@ static int exynos_pcie_host_init(struct pcie_port *pp)
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
        struct exynos_pcie *ep = to_exynos_pcie(pci);
 
+       pp->bridge->ops = &exynos_pci_ops;
+
        exynos_pcie_establish_link(ep);
        exynos_pcie_enable_interrupts(ep);
 
@@ -386,8 +393,6 @@ static int exynos_pcie_host_init(struct pcie_port *pp)
 }
 
 static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
-       .rd_own_conf = exynos_pcie_rd_own_conf,
-       .wr_own_conf = exynos_pcie_wr_own_conf,
        .host_init = exynos_pcie_host_init,
 };