[AArch64][SVE2] Add the SVE2.1 extract-and-narrow instructions

This patch adds the assembly/disassembly for the following instructions:

sqcvtn  : Signed saturating extract narrow and interleave
sqcvtun : Signed saturating unsigned extract narrow and interleave
uqcvtn  : Unsigned saturating extract narrow and interleave

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential revision: https://reviews.llvm.org/D136689

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 54be2d5..bb5a9a2 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3589,4 +3589,8 @@ def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>;
 
 defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">;
 defm PTRUE_C  : sve2p1_ptrue_pn<"ptrue">;
+
+defm SQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
+defm UQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>;
+defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>;
 } // End HasSVE2p1_or_HasSME2

diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 44a4865..76a79d2 100644 (file)
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -8739,3 +8739,27 @@ multiclass sve2p1_pred_as_ctr_to_mask<string mnemonic> {
  def _S : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b10, PPR32>;
  def _D : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b11, PPR64>;
 }
+
+
+// SME2 multi-vec extract narrow
+class sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc, bits<3> tsz>
+    : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn),
+        mnemonic, "\t$Zd, $Zn",
+        "", []>, Sched<[]> {
+  bits<5> Zd;
+  bits<4> Zn;
+  let Inst{31-23} = 0b010001010;
+  let Inst{22}    = tsz{2};
+  let Inst{21}    = 0b1;
+  let Inst{20-19} = tsz{1-0};
+  let Inst{18-13} = 0b001010;
+  let Inst{12-11} = opc;
+  let Inst{10}    = 0b0;
+  let Inst{9-6}   = Zn;
+  let Inst{5}     = 0b0;
+  let Inst{4-0}   = Zd;
+}
+
+multiclass sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc> {
+  def : sve2p1_multi_vec_extract_narrow<mnemonic, opc, 0b010>;
+}

diff --git a/llvm/test/MC/AArch64/SVE2p1/sqcvtn-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/sqcvtn-diagnostics.s
new file mode 100644 (file)
index 0000000..9f25036
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqcvtn-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqcvtn z0.h, {z0.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqcvtn z0.h, {z0.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqcvtn z0.h, {z1.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqcvtn z0.h, {z1.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffixes
+
+sqcvtn z0.b, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqcvtn z0.b, {z0.s-z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqcvtn z0.h, {z0.d-z1.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqcvtn z0.h, {z0.d-z1.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE2p1/sqcvtn.s b/llvm/test/MC/AArch64/SVE2p1/sqcvtn.s
new file mode 100644 (file)
index 0000000..5bb6636
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqcvtn.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+sqcvtn  z0.h, {z0.s-z1.s}  // 01000101-00110001-01000000-00000000
+// CHECK-INST: sqcvtn  z0.h, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0x40,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45314000 <unknown>
+
+sqcvtn  z21.h, {z10.s-z11.s}  // 01000101-00110001-01000001-01010101
+// CHECK-INST: sqcvtn  z21.h, { z10.s, z11.s }
+// CHECK-ENCODING: [0x55,0x41,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45314155 <unknown>
+
+sqcvtn  z23.h, {z12.s-z13.s}  // 01000101-00110001-01000001-10010111
+// CHECK-INST: sqcvtn  z23.h, { z12.s, z13.s }
+// CHECK-ENCODING: [0x97,0x41,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45314197 <unknown>
+
+sqcvtn  z31.h, {z30.s-z31.s}  // 01000101-00110001-01000011-11011111
+// CHECK-INST: sqcvtn  z31.h, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdf,0x43,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 453143df <unknown>

diff --git a/llvm/test/MC/AArch64/SVE2p1/sqcvtun-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/sqcvtun-diagnostics.s
new file mode 100644 (file)
index 0000000..8f2153b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqcvtun-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqcvtun z0.h, {z0.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqcvtun z0.h, {z0.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqcvtun z0.h, {z1.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqcvtun z0.h, {z1.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffixes
+
+sqcvtun z0.b, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqcvtun z0.b, {z0.s-z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqcvtun z0.h, {z0.d-z1.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqcvtun z0.h, {z0.d-z1.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE2p1/sqcvtun.s b/llvm/test/MC/AArch64/SVE2p1/sqcvtun.s
new file mode 100644 (file)
index 0000000..573da67
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sqcvtun.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+sqcvtun z0.h, {z0.s-z1.s}  // 01000101-00110001-01010000-00000000
+// CHECK-INST: sqcvtun z0.h, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0x50,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45315000 <unknown>
+
+sqcvtun z21.h, {z10.s-z11.s}  // 01000101-00110001-01010001-01010101
+// CHECK-INST: sqcvtun z21.h, { z10.s, z11.s }
+// CHECK-ENCODING: [0x55,0x51,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45315155 <unknown>
+
+sqcvtun z23.h, {z12.s-z13.s}  // 01000101-00110001-01010001-10010111
+// CHECK-INST: sqcvtun z23.h, { z12.s, z13.s }
+// CHECK-ENCODING: [0x97,0x51,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45315197 <unknown>
+
+sqcvtun z31.h, {z30.s-z31.s}  // 01000101-00110001-01010011-11011111
+// CHECK-INST: sqcvtun z31.h, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdf,0x53,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 453153df <unknown>

diff --git a/llvm/test/MC/AArch64/SVE2p1/uqcvtn-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/uqcvtn-diagnostics.s
new file mode 100644 (file)
index 0000000..a5e959e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uqcvtn-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uqcvtn z0.h, {z0.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqcvtn z0.h, {z0.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqcvtn z0.h, {z1.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: uqcvtn z0.h, {z1.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffixes
+
+uqcvtn z0.b, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqcvtn z0.b, {z0.s-z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqcvtn z0.h, {z0.d-z1.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqcvtn z0.h, {z0.d-z1.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE2p1/uqcvtn.s b/llvm/test/MC/AArch64/SVE2p1/uqcvtn.s
new file mode 100644 (file)
index 0000000..68be7a1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uqcvtn.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+uqcvtn  z0.h, {z0.s-z1.s}  // 01000101-00110001-01001000-00000000
+// CHECK-INST: uqcvtn  z0.h, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0x48,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45314800 <unknown>
+
+uqcvtn  z21.h, {z10.s-z11.s}  // 01000101-00110001-01001001-01010101
+// CHECK-INST: uqcvtn  z21.h, { z10.s, z11.s }
+// CHECK-ENCODING: [0x55,0x49,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45314955 <unknown>
+
+uqcvtn  z23.h, {z12.s-z13.s}  // 01000101-00110001-01001001-10010111
+// CHECK-INST: uqcvtn  z23.h, { z12.s, z13.s }
+// CHECK-ENCODING: [0x97,0x49,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45314997 <unknown>
+
+uqcvtn  z31.h, {z30.s-z31.s}  // 01000101-00110001-01001011-11011111
+// CHECK-INST: uqcvtn  z31.h, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdf,0x4b,0x31,0x45]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 45314bdf <unknown>