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ARM: dts: sun8i: r40: Add timer node
author
Jernej Skrabec
<jernej.skrabec@gmail.com>
Mon, 10 May 2021 16:36:47 +0000
(18:36 +0200)
committer
Maxime Ripard
<maxime@cerno.tech>
Tue, 18 May 2021 15:19:58 +0000
(17:19 +0200)
Allwinner R40 has a timer.
Add a node for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link:
https://lore.kernel.org/r/20210510163647.2731675-1-jernej.skrabec@gmail.com
arch/arm/boot/dts/sun8i-r40.dtsi
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diff --git
a/arch/arm/boot/dts/sun8i-r40.dtsi
b/arch/arm/boot/dts/sun8i-r40.dtsi
index 03e054c0bac40c8aaff7ea528682480a4922f026..291f4784e86c2e2c02bc5e352ae7adcf946e3620 100644
(file)
--- a/
arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/
arch/arm/boot/dts/sun8i-r40.dtsi
@@
-691,6
+691,18
@@
};
};
+ timer@1c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;