ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
if (ret) {
DRM_ERROR("Failed to retain power domain: %d\n", ret);
+ pm_runtime_put(&vc4_hdmi->pdev->dev);
return;
}
ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
if (ret) {
DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
+ pm_runtime_put(&vc4_hdmi->pdev->dev);
return;
}
ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
if (ret) {
DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
+ pm_runtime_put(&vc4_hdmi->pdev->dev);
return;
}
vc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);
if (IS_ERR(vc4_hdmi->hsm_req)) {
DRM_ERROR("Failed to set HSM clock rate: %ld\n", PTR_ERR(vc4_hdmi->hsm_req));
+ pm_runtime_put(&vc4_hdmi->pdev->dev);
return;
}
DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req));
clk_request_done(vc4_hdmi->hsm_req);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
+ pm_runtime_put(&vc4_hdmi->pdev->dev);
return;
}
clk_request_done(vc4_hdmi->bvb_req);
clk_request_done(vc4_hdmi->hsm_req);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
+ pm_runtime_put(&vc4_hdmi->pdev->dev);
return;
}