intel/genxml: Add L1 Cache Control bit field

Add L1 cache control bit field to RENDER_SURFACE_STATE and
STATE_BASE_ADDRESS instruction.

v1: (Jason)
- Add prefix to bit field
- Don't miss out STATE_BASE_ADDRESS instruction

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14676>

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index b24dd4e..78ed40f 100644 (file)
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -817,6 +817,13 @@
       <value name="GPU coherent" value="0"/>
       <value name="IA coherent" value="1"/>
     </field>
+    <field name="L1 Cache Control" start="176" end="178" type="uint" prefix="L1CC">
+      <value name="WBP" value="0"/>
+      <value name="UC" value="1"/>
+      <value name="WB" value="2"/>
+      <value name="WT" value="3"/>
+      <value name="WS" value="4"/>
+    </field>
     <field name="Tiled Resource Mode" start="178" end="179" type="uint">
       <value name="NONE" value="0"/>
       <value name="4KB" value="1"/>
@@ -6992,6 +6999,13 @@
     <field name="General State MOCS" start="36" end="42" type="uint" nonzero="true"/>
     <field name="General State Base Address" start="44" end="95" type="address"/>
     <field name="Stateless Data Port Access MOCS" start="112" end="118" type="uint" nonzero="true"/>
+    <field name="L1 Cache Control" start="119" end="121" type="uint" prefix="L1CC">
+      <value name="WBP" value="0"/>
+      <value name="UC" value="1"/>
+      <value name="WB" value="2"/>
+      <value name="WT" value="3"/>
+      <value name="WS" value="4"/>
+    </field>
     <field name="Surface State Base Address Modify Enable" start="128" end="128" type="bool"/>
     <field name="Surface State MOCS" start="132" end="138" type="uint" nonzero="true"/>
     <field name="Surface State Base Address" start="140" end="191" type="address"/>