* shader if all relevant channels have been discarded.
*/
fs_inst *discard_jump = bld.emit(FS_OPCODE_DISCARD_JUMP);
- discard_jump->flag_subreg = 1;
+ discard_jump->flag_subreg = sample_mask_flag_subreg(this);
discard_jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
discard_jump->predicate_inverse = true;
return brw_imm_ud(0xffffffff);
} else if (brw_wm_prog_data(v->stage_prog_data)->uses_kill) {
assert(bld.group() < 16 && bld.dispatch_width() <= 16);
- return brw_flag_reg(0, 1);
+ return brw_flag_subreg(sample_mask_flag_subreg(v));
} else {
assert(v->devinfo->gen >= 6 && bld.dispatch_width() <= 16);
return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
};
/**
+ * Return the flag register used in fragment shaders to keep track of live
+ * samples.
+ */
+static inline unsigned
+sample_mask_flag_subreg(const fs_visitor *shader)
+{
+ assert(shader->stage == MESA_SHADER_FRAGMENT);
+ return 1;
+}
+
+/**
* The fragment shader code generator.
*
* Translates FS IR to actual i965 assembly code.
fs_inst *mov = bld.MOV(dest, brw_imm_ud(~0));
mov->predicate = BRW_PREDICATE_NORMAL;
mov->predicate_inverse = true;
- mov->flag_subreg = 1;
+ mov->flag_subreg = sample_mask_flag_subreg(this);
break;
}
}
cmp->predicate = BRW_PREDICATE_NORMAL;
- cmp->flag_subreg = 1;
+ cmp->flag_subreg = sample_mask_flag_subreg(this);
if (devinfo->gen >= 6) {
/* Due to the way we implement discard, the jump will only happen
if (prog_data->uses_kill) {
write->predicate = BRW_PREDICATE_NORMAL;
- write->flag_subreg = 1;
+ write->flag_subreg = sample_mask_flag_subreg(this);
}
return write;