drm/i915: print computed bpp in dp link configuration

Pretty useful to debug our DP bandwidth woes.

v2: Also print out the required and available link bandwidth,
suggested by Chris Wilson.

v3: Also print out the input parameters so that diagnosing failures to
find a valid dp link configuration is possible.

v4: s/Display port/DP/ to shorten the output.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 44cf32c..22c66b7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -688,7 +688,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
        int lane_count, clock;
        int max_lane_count = intel_dp_max_lane_count(intel_dp);
        int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
-       int bpp;
+       int bpp, mode_rate;
        static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 
        if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
@@ -702,24 +702,30 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
                mode->clock = intel_dp->panel_fixed_mode->clock;
        }
 
+       DRM_DEBUG_KMS("DP link computation with max lane count %i "
+                     "max bw %02x pixel clock %iKHz\n",
+                     max_lane_count, bws[max_clock], mode->clock);
+
        if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
                return false;
 
        bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
+       mode_rate = intel_dp_link_required(mode->clock, bpp);
 
        for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
                for (clock = 0; clock <= max_clock; clock++) {
                        int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 
-                       if (intel_dp_link_required(mode->clock, bpp)
-                                       <= link_avail) {
+                       if (mode_rate <= link_avail) {
                                intel_dp->link_bw = bws[clock];
                                intel_dp->lane_count = lane_count;
                                adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
-                               DRM_DEBUG_KMS("Display port link bw %02x lane "
-                                               "count %d clock %d\n",
+                               DRM_DEBUG_KMS("DP link bw %02x lane "
+                                               "count %d clock %d bpp %d\n",
                                       intel_dp->link_bw, intel_dp->lane_count,
-                                      adjusted_mode->clock);
+                                      adjusted_mode->clock, bpp);
+                               DRM_DEBUG_KMS("DP link bw required %i available %i\n",
+                                             mode_rate, link_avail);
                                return true;
                        }
                }