r600: move non-surface related depth state to general state

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index e5e0f55..083b997 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -138,6 +138,19 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(CB_CLRCMP_MSK);
     LINK_STATES(CB_BLEND_CONTROL);
 
+    //DB
+    LINK_STATES(DB_HTILE_DATA_BASE);
+    LINK_STATES(DB_STENCIL_CLEAR);
+    LINK_STATES(DB_DEPTH_CLEAR);
+    LINK_STATES(DB_STENCILREFMASK);
+    LINK_STATES(DB_STENCILREFMASK_BF);
+    LINK_STATES(DB_DEPTH_CONTROL);
+    LINK_STATES(DB_SHADER_CONTROL);
+    LINK_STATES(DB_RENDER_CONTROL);
+    LINK_STATES(DB_RENDER_OVERRIDE);
+    LINK_STATES(DB_HTILE_SURFACE);
+    LINK_STATES(DB_ALPHA_TO_MASK);
+
     // SX
     LINK_STATES(SX_MISC);
     LINK_STATES(SX_ALPHA_TEST_CONTROL);
@@ -491,37 +504,16 @@ GLboolean r700SendDepthTargetState(context_t *context)
                return GL_FALSE;
        }
 
-        BEGIN_BATCH_NO_AUTOSTATE(9);
+        BEGIN_BATCH_NO_AUTOSTATE(8);
        R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
        R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
        R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
-       R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 3);
+       R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
        R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
                             rrb->bo,
                             r700->DB_DEPTH_BASE.u32All,
                             0, RADEON_GEM_DOMAIN_VRAM, 0);
        R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
-       R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All);
-        END_BATCH();
-
-        BEGIN_BATCH_NO_AUTOSTATE(24);
-       R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
-       R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
-       R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
-
-       R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
-       R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
-       R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
-
-       R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
-       R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
-
-       R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
-       R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
-       R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
-
-       R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
-       R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
         END_BATCH();
 
        COMMIT_BATCH();