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perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont
author
Kan Liang
<kan.liang@linux.intel.com>
Fri, 1 May 2020 12:54:42 +0000
(
05:54
-0700)
committer
Peter Zijlstra
<peterz@infradead.org>
Tue, 19 May 2020 18:34:16 +0000
(20:34 +0200)
The mask in the extra_regs for Intel Tremont need to be extended to
allow more defined bits.
"Outstanding Requests" (bit 63) is only available on MSR_OFFCORE_RSP0;
Fixes:
6daeb8737f8a
("perf/x86/intel: Add Tremont core PMU support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link:
https://lkml.kernel.org/r/20200501125442.7030-1-kan.liang@linux.intel.com
arch/x86/events/intel/core.c
patch
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diff --git
a/arch/x86/events/intel/core.c
b/arch/x86/events/intel/core.c
index
332954c
..
ca35c8b
100644
(file)
--- a/
arch/x86/events/intel/core.c
+++ b/
arch/x86/events/intel/core.c
@@
-1892,8
+1892,8
@@
static __initconst const u64 tnt_hw_cache_extra_regs
static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
- INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0),
- INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1),
+ INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x
800ff0
ffffff9fffull, RSP_0),
+ INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff
0ff
ffff9fffull, RSP_1),
EVENT_EXTRA_END
};