PCI: dwc: Add support to enable CDM register check
authorVidya Sagar <vidyas@nvidia.com>
Tue, 13 Aug 2019 11:36:22 +0000 (17:06 +0530)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tue, 13 Aug 2019 15:00:46 +0000 (16:00 +0100)
Add support to enable CDM (Configuration Dependent Module) register
check for any data corruption based on the DT property
'snps,enable-cdm-check'.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
drivers/pci/controller/dwc/pcie-designware.c
drivers/pci/controller/dwc/pcie-designware.h

index 1d87e82..59eaeeb 100644 (file)
@@ -547,4 +547,11 @@ void dw_pcie_setup(struct dw_pcie *pci)
                break;
        }
        dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
+       if (of_property_read_bool(np, "snps,enable-cdm-check")) {
+               val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
+               val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
+                      PCIE_PL_CHK_REG_CHK_REG_START;
+               dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
+       }
 }
index 11c2234..5a18e94 100644 (file)
 #define PCIE_MISC_CONTROL_1_OFF                0x8BC
 #define PCIE_DBI_RO_WR_EN              BIT(0)
 
+#define PCIE_PL_CHK_REG_CONTROL_STATUS                 0xB20
+#define PCIE_PL_CHK_REG_CHK_REG_START                  BIT(0)
+#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS             BIT(1)
+#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR       BIT(16)
+#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR            BIT(17)
+#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE               BIT(18)
+
+#define PCIE_PL_CHK_REG_ERR_ADDR                       0xB28
+
 /*
  * iATU Unroll-specific register definitions
  * From 4.80 core version the address translation will be made by unroll