arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 node
authorShazad Hussain <quic_shazhuss@quicinc.com>
Fri, 26 May 2023 13:31:17 +0000 (19:01 +0530)
committerBjorn Andersson <andersson@kernel.org>
Sat, 27 May 2023 01:12:26 +0000 (18:12 -0700)
Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-2-quic_shazhuss@quicinc.com
arch/arm64/boot/dts/qcom/sa8775p.dtsi

index 07aeb8a..74bd5f3 100644 (file)
                        };
                };
 
+               qupv3_id_0: geniqup@9c0000 {
+                       compatible = "qcom,geni-se-qup";
+                       reg = <0x0 0x9c0000 0x0 0x6000>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       clock-names = "m-ahb", "s-ahb";
+                       clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+                               <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+                       iommus = <&apps_smmu 0x403 0x0>;
+                       status = "disabled";
+               };
+
                qupv3_id_1: geniqup@ac0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0x0 0x00ac0000 0x0 0x6000>;
                        };
                };
 
+               qupv3_id_3: geniqup@bc0000 {
+                       compatible = "qcom,geni-se-qup";
+                       reg = <0x0 0xbc0000 0x0 0x6000>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       clock-names = "m-ahb", "s-ahb";
+                       clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
+                               <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
+                       iommus = <&apps_smmu 0x43 0x0>;
+                       status = "disabled";
+               };
+
                ufs_mem_hc: ufs@1d84000 {
                        compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
                        reg = <0x0 0x01d84000 0x0 0x3000>;