dt-bindings: Add HDA support for Tegra234
authorMohan Kumar <mkumard@nvidia.com>
Wed, 16 Feb 2022 09:22:38 +0000 (14:52 +0530)
committerThierry Reding <treding@nvidia.com>
Thu, 24 Feb 2022 17:34:33 +0000 (18:34 +0100)
Add hda clocks, memory ,power and reset binding entries
for Tegra234.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
include/dt-bindings/clock/tegra234-clock.h
include/dt-bindings/memory/tegra234-mc.h
include/dt-bindings/power/tegra234-powergate.h
include/dt-bindings/reset/tegra234-reset.h

index 5c201a8..0c38769 100644 (file)
 #define TEGRA234_CLK_PLLC4                     237U
 /** @brief 32K input clock provided by PMIC */
 #define TEGRA234_CLK_CLK_32K                   289U
+/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
+#define TEGRA234_CLK_AZA_2XBIT                 457U
+/** @brief aza_2xbitclk / 2 (aza_bitclk) */
+#define TEGRA234_CLK_AZA_BIT                   458U
 #endif
index 42661dd..672b953 100644 (file)
@@ -10,6 +10,7 @@
 
 /* NISO0 stream IDs */
 #define TEGRA234_SID_APE       0x02
+#define TEGRA234_SID_HDA       0x03
 
 /* NISO1 stream IDs */
 #define TEGRA234_SID_SDMMC4    0x02
  * memory client IDs
  */
 
+/* High-definition audio (HDA) read clients */
+#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
+/* High-definition audio (HDA) write clients */
+#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
 /* sdmmcd memory read client */
 #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
 /* sdmmcd memory write client */
index 8e28fcb..a635a8b 100644 (file)
@@ -5,5 +5,6 @@
 #define __ABI_MACH_T234_POWERGATE_T234_H_
 
 #define TEGRA234_POWER_DOMAIN_AUD      2U
+#define TEGRA234_POWER_DOMAIN_DISP     3U
 
 #endif
index ba390b8..178e73a 100644 (file)
@@ -10,6 +10,8 @@
  * @brief Identifiers for Resets controllable by firmware
  * @{
  */
+#define TEGRA234_RESET_HDA                     20U
+#define TEGRA234_RESET_HDACODEC                        21U
 #define TEGRA234_RESET_I2C1                    24U
 #define TEGRA234_RESET_I2C2                    29U
 #define TEGRA234_RESET_I2C3                    30U