#define TEGRA234_CLK_PLLC4 237U
/** @brief 32K input clock provided by PMIC */
#define TEGRA234_CLK_CLK_32K 289U
+/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
+#define TEGRA234_CLK_AZA_2XBIT 457U
+/** @brief aza_2xbitclk / 2 (aza_bitclk) */
+#define TEGRA234_CLK_AZA_BIT 458U
#endif
/* NISO0 stream IDs */
#define TEGRA234_SID_APE 0x02
+#define TEGRA234_SID_HDA 0x03
/* NISO1 stream IDs */
#define TEGRA234_SID_SDMMC4 0x02
* memory client IDs
*/
+/* High-definition audio (HDA) read clients */
+#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
+/* High-definition audio (HDA) write clients */
+#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
/* sdmmcd memory read client */
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
/* sdmmcd memory write client */
#define __ABI_MACH_T234_POWERGATE_T234_H_
#define TEGRA234_POWER_DOMAIN_AUD 2U
+#define TEGRA234_POWER_DOMAIN_DISP 3U
#endif
* @brief Identifiers for Resets controllable by firmware
* @{
*/
+#define TEGRA234_RESET_HDA 20U
+#define TEGRA234_RESET_HDACODEC 21U
#define TEGRA234_RESET_I2C1 24U
#define TEGRA234_RESET_I2C2 29U
#define TEGRA234_RESET_I2C3 30U