ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
+M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
S: Maintainted
T: git git://git.denx.de/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
+ imply SPL
+ imply SPL_DM
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC_SUPPORT
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
if ARCH_SOCFPGA
+config NR_DRAM_BANKS
+ default 1
+
+config SPL_STACK_R_ADDR
+ default 0x00800000 if TARGET_SOCFPGA_GEN5
+
+config SPL_SYS_MALLOC_F_LEN
+ default 0x800 if TARGET_SOCFPGA_GEN5
+
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
+config SYS_MALLOC_F_LEN
+ default 0x2000 if TARGET_SOCFPGA_ARRIA10
+ default 0x2000 if TARGET_SOCFPGA_GEN5
+
+config SYS_TEXT_BASE
+ default 0x01000040 if TARGET_SOCFPGA_ARRIA10
+ default 0x01000040 if TARGET_SOCFPGA_GEN5
+
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
select SYSCON
select SPL_SYSCON if SPL
select ETH_DESIGNWARE_SOCFPGA
+ imply FPGA_SOCFPGA
+ imply USE_TINY_PRINTF
config TARGET_SOCFPGA_CYCLONE5
bool
config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
+ imply FPGA_SOCFPGA
+ imply SPL_STACK_R
+ imply SPL_SYS_MALLOC_SIMPLE
+ imply USE_TINY_PRINTF
config TARGET_SOCFPGA_STRATIX10
bool
cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
/* if command buffer is full or not enough free space
- * to fit the data
+ * to fit the data. Note, len is in u32 unit.
*/
if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
- MBOX_CMD_BUFFER_SIZE) < len)
+ MBOX_CMD_BUFFER_SIZE) < (len + 1))
return -ENOMEM;
/* write header to circular buffer */
0x00018004,
0x06001209,
0x00004000,
- 0x20002412,
+ 0x20042412,
0x00904800,
0x00000030,
0x80000000,
u32 serial;
int ret;
- /* EEPROM is at bus 0. */
- ret = i2c_set_bus_num(0);
- if (ret) {
- puts("Cannot select EEPROM I2C bus.\n");
- return 0;
- }
-
- /* EEPROM is at address 0x50. */
+ /* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */
ret = eeprom_read(0x50, 0, data, sizeof(data));
if (ret) {
puts("Cannot read I2C EEPROM.\n");
config CMD_EEPROM
bool "eeprom - EEPROM subsystem"
- depends on !DM_I2C || DM_I2C_COMPAT
help
(deprecated, needs conversion to driver model)
Provides commands to read and write EEPROM (Electrically Erasable
#endif
#endif
+#if defined(CONFIG_DM_I2C)
+int eeprom_i2c_bus;
+#endif
+
__weak int eeprom_write_enable(unsigned dev_addr, int state)
{
return 0;
void eeprom_init(int bus)
{
/* I2C EEPROM */
-#if defined(CONFIG_SYS_I2C)
+#if defined(CONFIG_DM_I2C)
+ eeprom_i2c_bus = bus;
+#elif defined(CONFIG_SYS_I2C)
if (bus >= 0)
i2c_set_bus_num(bus);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
{
int ret = 0;
-#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS)
+#if defined(CONFIG_DM_I2C)
struct udevice *dev;
- ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS, addr[0],
+ ret = i2c_get_chip_for_busnum(eeprom_i2c_bus, addr[0],
alen - 1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
- CONFIG_SYS_I2C_EEPROM_BUS);
+ eeprom_i2c_bus);
return CMD_RET_FAILURE;
}
ret = dm_i2c_write(dev, offset, buffer, len);
#else /* Non DM I2C support - will be removed */
-#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
- i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-#endif
if (read)
ret = i2c_read(addr[0], offset, alen - 1, buffer, len);
else
ret = i2c_write(addr[0], offset, alen - 1, buffer, len);
-#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */
+#endif /* CONFIG_DM_I2C */
if (ret)
ret = CMD_RET_FAILURE;
int rcode = 0;
uchar addr[3];
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+ eeprom_init(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
+
while (offset < end) {
alen = eeprom_addr(dev_addr, offset, addr);
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
-CONFIG_USE_TINY_PRINTF=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_IS1=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SR1500=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_RESET=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SYS_TEXT_BASE=0x1000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
-CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS3=y
CONFIG_LED_STATUS_BIT3=65
CONFIG_LED_STATUS_CMD=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias ptomsich Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
alias sbabic Stefano Babic <sbabic@denx.de>
+alias simongoldschmidt Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
alias sjg Simon Glass <sjg@chromium.org>
alias smcnutt Scott McNutt <smcnutt@psyent.com>
alias stroese Stefan Roese <sr@denx.de>
alias s5pc samsung
alias samsung uboot, prom
alias snapdragon uboot, mateusz
-alias socfpga uboot, marex, dinh
+alias socfpga uboot, marex, dinh, simongoldschmidt
alias sunxi uboot, jagan, maxime
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
struct dw_i2c {
struct i2c_regs *regs;
struct dw_scl_sda_cfg *scl_sda_cfg;
- struct reset_ctl reset_ctl;
+ struct reset_ctl_bulk resets;
};
#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
}
- ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl);
+ ret = reset_get_bulk(bus, &priv->resets);
if (ret)
- pr_info("reset_get_by_name() failed: %d\n", ret);
-
- if (&priv->reset_ctl)
- reset_deassert(&priv->reset_ctl);
+ dev_warn(bus, "Can't get reset: %d\n", ret);
+ else
+ reset_deassert_bulk(&priv->resets);
return __dw_i2c_init(priv->regs, 0, 0);
}
+static int designware_i2c_remove(struct udevice *dev)
+{
+ struct dw_i2c *priv = dev_get_priv(dev);
+
+ return reset_release_bulk(&priv->resets);
+}
+
static int designware_i2c_bind(struct udevice *dev)
{
static int num_cards;
.bind = designware_i2c_bind,
.probe = designware_i2c_probe,
.priv_auto_alloc_size = sizeof(struct dw_i2c),
+ .remove = designware_i2c_remove,
+ .flags = DM_FLAG_OS_PREPARE,
.ops = &designware_i2c_ops,
};
return ret;
}
+/*
+ * Make sure HT bit is cleared. This bit is set on entering battery backup
+ * mode, so do this before the first read access.
+ */
+static int m41t62_rtc_probe(struct udevice *dev)
+{
+ return m41t62_rtc_reset(dev);
+}
+
static const struct rtc_ops m41t62_rtc_ops = {
.get = m41t62_rtc_get,
.set = m41t62_rtc_set,
static const struct udevice_id m41t62_rtc_ids[] = {
{ .compatible = "st,m41t62" },
+ { .compatible = "st,m41t82" },
{ .compatible = "microcrystal,rv4162" },
{ }
};
.id = UCLASS_RTC,
.of_match = m41t62_rtc_ids,
.ops = &m41t62_rtc_ops,
+ .probe = &m41t62_rtc_probe,
};
#else /* NON DM RTC code - will be removed */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000
-/* Ethernet on SoC (EMAC) */
-
-/*
- * U-Boot environment configurations
- */
-
/*
* Serial / UART configurations
*/
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Ethernet on SoC (EMAC) */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
*/
#define CONFIG_CLOCKS
-#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
-
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE)
#endif
/*
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)))
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
+#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
#else
-#define CONFIG_SYS_INIT_SP_ADDR \
+#define CONFIG_SPL_STACK \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#endif
+/*
+ * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
+ * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
+ * in U-Boot pre-reloc is higher than in SPL.
+ */
+#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
+#else
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
+#endif
+
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-#ifndef CONFIG_SYS_HOSTNAME
-#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
-#endif
-
/*
* Cache
*/
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
- * EPCS/EPCQx1 Serial Flash Controller
- */
-#ifdef CONFIG_ALTERA_SPI
-/*
- * The base address is configurable in QSys, each board must specify the
- * base address based on it's particular FPGA configuration. Please note
- * that the address here is incremented by 0x400 from the Base address
- * selected in QSys, since the SPI registers are at offset +0x400.
- * #define CONFIG_SYS_SPI_BASE 0xff240400
- */
-#endif
-
-/*
* Ethernet on SoC (EMAC)
*/
#ifdef CONFIG_CMD_NET
#endif
/*
- * I2C support
- */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
-#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
-#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
-#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
-/* Using standard mode which the speed up to 100Kb/s */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SPEED1 100000
-#define CONFIG_SYS_I2C_SPEED2 100000
-#define CONFIG_SYS_I2C_SPEED3 100000
-/* Address of device when used as slave */
-#define CONFIG_SYS_I2C_SLAVE 0x02
-#define CONFIG_SYS_I2C_SLAVE1 0x02
-#define CONFIG_SYS_I2C_SLAVE2 0x02
-#define CONFIG_SYS_I2C_SLAVE3 0x02
-#ifndef __ASSEMBLY__
-/* Clock supplied to I2C controller in unit of MHz */
-unsigned int cm_get_l4_sp_clk_hz(void);
-#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
-#endif
-#endif /* CONFIG_DM_I2C */
-
-/*
* QSPI support
*/
/* Enable multiple SPI NOR flash manufacturers */
#endif
/*
- * Designware SPI support
- */
-
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_NS16550_SERIAL
-
-/*
* USB
*/
#endif
/*
- * mtd partitioning for serial NOR flash
- *
- * device nor0 <ff705000.spi.0>, # parts = 6
- * #: name size offset mask_flags
- * 0: u-boot 0x00100000 0x00000000 0
- * 1: env1 0x00040000 0x00100000 0
- * 2: env2 0x00040000 0x00140000 0
- * 3: UBI 0x03e80000 0x00180000 0
- * 4: boot 0x00e80000 0x00180000 0
- * 5: rootfs 0x01000000 0x01000000 0
- *
- */
-
-/*
* SPL
*
* SRAM Memory layout for gen 5:
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
- * 0xFFFF_yyyy ...... Malloc area
- * 0xFFFF_zzzz ...... Global Data
- * 0xFFFF_FF00 ...... End of SRAM
+ * 0xFFFF_yyyy ...... Global Data
+ * 0xFFFF_zzzz ...... Malloc area
+ * 0xFFFF_FFFF ...... End of SRAM
*
* SRAM Memory layout for Arria 10:
* 0xFFE0_0000 ...... Start of SRAM (bottom)
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#endif
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-/* SPL memory allocation configuration, this is for FAT implementation */
-#ifndef CONFIG_SYS_SPL_MALLOC_START
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
- CONFIG_SYS_SPL_MALLOC_SIZE + \
- CONFIG_SYS_INIT_RAM_ADDR)
-#endif
-#endif
-
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#endif
#endif
-/*
- * Stack setup
- */
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
-#endif
-
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Ethernet on SoC (EMAC) */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Ethernet on SoC (EMAC) */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Ethernet on SoC (EMAC) */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Ethernet on SoC (EMAC) */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_ARP_TIMEOUT 500UL
-
-/* PHY */
#endif
/* The rest of the configuration is shared */
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Ethernet on SoC (EMAC) */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Ethernet on SoC (EMAC) */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* The PHY is autodetected, so no MII PHY address is needed here */
#define PHY_ANEG_TIMEOUT 8000
-/* Environment */
-
/* Enable SPI NOR flash reset, needed for SPI booting */
#define CONFIG_SPI_N25Q256A_RESET
#define CONFIG_ENV_OFFSET 0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-/*
- * The QSPI NOR flash layout on SR1500:
- *
- * 0000.0000 - 0003.ffff: SPL (4 times)
- * 0004.0000 - 000d.ffff: U-Boot
- * 000e.0000 - 000e.ffff: env1
- * 000f.0000 - 000f.ffff: env2
- */
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* I2C EEPROM */
-#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 0
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-#endif
-
-/*
- * Status LEDs:
- * 0 ... Top Green
- * 1 ... Top Red
- * 2 ... Bottom Green
- * 3 ... Bottom Red
- */
-
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_BOOTP_SEND_HOSTNAME
-/* PHY */
#endif
/* Extra Environment */