ARM: dts: stm32: add ADC support on stm32h743

Add support for ADC (Analog to Digital Converter) to STM32H743.
It has 3 ADCs, distributed over two ADC blocks:
- ADC1 and ADC2 @0x40022000
- ADC3 @0x58026000 (instantiated separately)

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index c93b48f..1da54ff 100644 (file)
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -106,6 +106,59 @@
                        clocks = <&timer_clk>;
 
                };
+
+               adc_12: adc@40022000 {
+                       compatible = "st,stm32h7-adc-core";
+                       reg = <0x40022000 0x400>;
+                       interrupts = <18>;
+                       clocks = <&timer_clk>;
+                       clock-names = "bus";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+
+                       adc1: adc@0 {
+                               compatible = "st,stm32h7-adc";
+                               #io-channel-cells = <1>;
+                               reg = <0x0>;
+                               interrupt-parent = <&adc_12>;
+                               interrupts = <0>;
+                               status = "disabled";
+                       };
+
+                       adc2: adc@100 {
+                               compatible = "st,stm32h7-adc";
+                               #io-channel-cells = <1>;
+                               reg = <0x100>;
+                               interrupt-parent = <&adc_12>;
+                               interrupts = <1>;
+                               status = "disabled";
+                       };
+               };
+
+               adc_3: adc@58026000 {
+                       compatible = "st,stm32h7-adc-core";
+                       reg = <0x58026000 0x400>;
+                       interrupts = <127>;
+                       clocks = <&timer_clk>;
+                       clock-names = "bus";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+
+                       adc3: adc@0 {
+                               compatible = "st,stm32h7-adc";
+                               #io-channel-cells = <1>;
+                               reg = <0x0>;
+                               interrupt-parent = <&adc_3>;
+                               interrupts = <0>;
+                               status = "disabled";
+                       };
+               };
        };
 };