arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller

As of now, all of the boards based on the cherry platform have a
usable secondary SD/MMC controller, usually for SD cards: enable
it to allow both booting from it and generally accessing external
storage.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220902081156.38526-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 1174ab3..0654a28 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -17,6 +17,7 @@
                i2c5 = &i2c5;
                i2c7 = &i2c7;
                mmc0 = &mmc0;
+               mmc1 = &mmc1;
                serial0 = &uart0;
        };
 
@@ -227,6 +228,24 @@
        vqmmc-supply = <&mt6359_vufs_ldo_reg>;
 };
 
+&mmc1 {
+       status = "okay";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
+       max-frequency = <200000000>;
+       no-mmc;
+       no-sdio;
+       pinctrl-names = "default", "state_uhs";
+       pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>;
+       pinctrl-1 = <&mmc1_pins_default>;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
+       vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
+};
+
 /* for CPU-L */
 &mt6359_vcore_buck_reg {
        regulator-always-on;
@@ -575,6 +594,32 @@
                };
        };
 
+       mmc1_pins_detect: mmc1-detect-pins {
+               pins-insert {
+                       pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
+                       bias-pull-up;
+               };
+       };
+
+       mmc1_pins_default: mmc1-default-pins {
+               pins-cmd-dat {
+                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
+                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
+                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
+                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
+                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
+                       input-enable;
+                       drive-strength = <8>;
+                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+               };
+
+               pins-clk {
+                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
+                       drive-strength = <8>;
+                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+               };
+       };
+
        nor_pins_default: nor-default-pins {
                pins-ck-io {
                        pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,