accel/habanalabs: in hw_fini return error code if polling timed-out
authorDafna Hirschfeld <dhirschfeld@habana.ai>
Mon, 20 Feb 2023 08:09:25 +0000 (10:09 +0200)
committerOded Gabbay <ogabbay@kernel.org>
Mon, 20 Mar 2023 15:35:29 +0000 (17:35 +0200)
In hw_fini callback, we use either the cpucp packet method or polling a
register. Currently we return error only in the case of cpucp packet
failure. In this patch we also return error if polling timed out.

Signed-off-by: Dafna Hirschfeld <dhirschfeld@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
drivers/accel/habanalabs/gaudi/gaudi.c
drivers/accel/habanalabs/gaudi2/gaudi2.c
drivers/accel/habanalabs/goya/goya.c

index 004846b..a9d8467 100644 (file)
@@ -4206,10 +4206,10 @@ skip_reset:
        msleep(reset_timeout_ms);
 
        status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
-       if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
-               dev_err(hdev->dev,
-                       "Timeout while waiting for device to reset 0x%x\n",
-                       status);
+       if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) {
+               dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status);
+               return -ETIMEDOUT;
+       }
 
        if (gaudi) {
                gaudi->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | HW_CAP_HBM |
index 652f12a..15a06be 100644 (file)
@@ -6036,7 +6036,7 @@ static void gaudi2_execute_hard_reset(struct hl_device *hdev, u32 reset_sleep_ms
        WREG32(mmPSOC_RESET_CONF_SW_ALL_RST, 1);
 }
 
-static void gaudi2_get_soft_rst_done_indication(struct hl_device *hdev, u32 poll_timeout_us)
+static int gaudi2_get_soft_rst_done_indication(struct hl_device *hdev, u32 poll_timeout_us)
 {
        int i, rc = 0;
        u32 reg_val;
@@ -6053,6 +6053,7 @@ static void gaudi2_get_soft_rst_done_indication(struct hl_device *hdev, u32 poll
        if (rc)
                dev_err(hdev->dev, "Timeout while waiting for FW to complete soft reset (0x%x)\n",
                                reg_val);
+       return rc;
 }
 
 /**
@@ -6065,7 +6066,7 @@ static void gaudi2_get_soft_rst_done_indication(struct hl_device *hdev, u32 poll
  *
  * This function executes soft reset based on if driver/FW should do the reset
  */
-static void gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms,
+static int gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms,
                                                bool driver_performs_reset, u32 poll_timeout_us)
 {
        struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
@@ -6079,8 +6080,8 @@ static void gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms
 
                WREG32(le32_to_cpu(dyn_regs->gic_host_soft_rst_irq),
                        gaudi2_irq_map_table[GAUDI2_EVENT_CPU_SOFT_RESET].cpu_id);
-               gaudi2_get_soft_rst_done_indication(hdev, poll_timeout_us);
-               return;
+
+               return gaudi2_get_soft_rst_done_indication(hdev, poll_timeout_us);
        }
 
        /* Block access to engines, QMANs and SM during reset, these
@@ -6095,6 +6096,7 @@ static void gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms
                                mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE + HL_BLOCK_SIZE);
 
        WREG32(mmPSOC_RESET_CONF_SOFT_RST, 1);
+       return 0;
 }
 
 static void gaudi2_poll_btm_indication(struct hl_device *hdev, u32 reset_sleep_ms,
index e02de93..07d6787 100644 (file)
@@ -2834,10 +2834,10 @@ static int goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
        msleep(reset_timeout_ms);
 
        status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
-       if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
-               dev_err(hdev->dev,
-                       "Timeout while waiting for device to reset 0x%x\n",
-                       status);
+       if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) {
+               dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status);
+               return -ETIMEDOUT;
+       }
 
        if (!hard_reset && goya) {
                goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |